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Differential D109253 Diff 370649 llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

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llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

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; CHECK-NEXT: sub x10, x10, #1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1b { z1.b }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1b { z0.b }, p0, [sp] ; CHECK-NEXT: st1b { z0.b }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldrb w0, [x8, x9] ; CHECK-NEXT: ldrb w0, [x8, x9]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 32 x i8> %a, i32 %idx %ext = extractelement <vscale x 32 x i8> %a, i32 %idx
ret i8 %ext ret i8 %ext
} }
define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) { define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) {
; CHECK-LABEL: split_extract_16i16_idx: ; CHECK-LABEL: split_extract_16i16_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: rdvl x10, #1 ; CHECK-NEXT: rdvl x10, #1
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1] ; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i16> %a, i32 %idx %ext = extractelement <vscale x 16 x i16> %a, i32 %idx
ret i16 %ext ret i16 %ext
} }
define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) { define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) {
; CHECK-LABEL: split_extract_8i32_idx: ; CHECK-LABEL: split_extract_8i32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cnth x10 ; CHECK-NEXT: cnth x10
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x9, w0 ; CHECK-NEXT: sxtw x9, w0
; CHECK-NEXT: sub x10, x10, #1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldr w0, [x8, x9, lsl #2] ; CHECK-NEXT: ldr w0, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 8 x i32> %a, i32 %idx %ext = extractelement <vscale x 8 x i32> %a, i32 %idx
ret i32 %ext ret i32 %ext
} }
define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) { define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) {
; CHECK-LABEL: split_extract_8i64_idx: ; CHECK-LABEL: split_extract_8i64_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 9 Lines
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: st1d { z3.d }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1d { z3.d }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1d { z2.d }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x9, x9, x10, lo ; CHECK-NEXT: csel x9, x9, x10, lo
; CHECK-NEXT: ldr x0, [x8, x9, lsl #3] ; CHECK-NEXT: ldr x0, [x8, x9, lsl #3]
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 8 x i64> %a, i32 %idx %ext = extractelement <vscale x 8 x i64> %a, i32 %idx
ret i64 %ext ret i64 %ext
} }
; EXTRACT VECTOR ELT, CONSTANT IDX ; EXTRACT VECTOR ELT, CONSTANT IDX
define i16 @promote_extract_4i16(<vscale x 4 x i16> %a) { define i16 @promote_extract_4i16(<vscale x 4 x i16> %a) {
Show All 26 Lines
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #128 ; CHECK-NEXT: mov w9, #128
; CHECK-NEXT: cmp x10, #128 ; CHECK-NEXT: cmp x10, #128
; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1h { z1.h }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1h { z0.h }, p0, [sp] ; CHECK-NEXT: st1h { z0.h }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1] ; CHECK-NEXT: ldrh w0, [x8, x9, lsl #1]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i16> %a, i32 128 %ext = extractelement <vscale x 16 x i16> %a, i32 128
ret i16 %ext ret i16 %ext
} }
define i32 @split_extract_16i32(<vscale x 16 x i32> %a) { define i32 @split_extract_16i32(<vscale x 16 x i32> %a) {
; CHECK-LABEL: split_extract_16i32: ; CHECK-LABEL: split_extract_16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 9 Lines
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: cmp x10, x9 ; CHECK-NEXT: cmp x10, x9
; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [sp] ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldr w0, [x8, x9, lsl #2] ; CHECK-NEXT: ldr w0, [x8, x9, lsl #2]
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 16 x i32> %a, i32 100000 %ext = extractelement <vscale x 16 x i32> %a, i32 100000
ret i32 %ext ret i32 %ext
} }
define i64 @split_extract_4i64(<vscale x 4 x i64> %a) { define i64 @split_extract_4i64(<vscale x 4 x i64> %a) {
; CHECK-LABEL: split_extract_4i64: ; CHECK-LABEL: split_extract_4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2 ; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: cntw x10 ; CHECK-NEXT: cntw x10
; CHECK-NEXT: sub x10, x10, #1 ; CHECK-NEXT: sub x10, x10, #1
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov w9, #10 ; CHECK-NEXT: mov w9, #10
; CHECK-NEXT: cmp x10, #10 ; CHECK-NEXT: cmp x10, #10
; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: csel x9, x10, x9, lo ; CHECK-NEXT: csel x9, x10, x9, lo
; CHECK-NEXT: ldr x0, [x8, x9, lsl #3] ; CHECK-NEXT: ldr x0, [x8, x9, lsl #3]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext = extractelement <vscale x 4 x i64> %a, i32 10 %ext = extractelement <vscale x 4 x i64> %a, i32 10
ret i64 %ext ret i64 %ext
} }