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Differential D109253 Diff 370649 llvm/test/CodeGen/AArch64/sve-insert-vector.ll

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llvm/test/CodeGen/AArch64/sve-insert-vector.ll

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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8, #2, mul vl] ; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8, #2, mul vl]
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8, #3, mul vl] ; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8, #3, mul vl]
; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp]
; CHECK-NEXT: st1d { z2.d }, p0, [x0, #3, mul vl] ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #3, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x0, #2, mul vl] ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #2, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
; CHECK-NEXT: st1d { z3.d }, p0, [x0] ; CHECK-NEXT: st1d { z3.d }, p0, [x0]
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
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; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: str q0, [sp, #16] ; CHECK-NEXT: str q0, [sp, #16]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp] ; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp]
; CHECK-NEXT: st1d { z0.d }, p0, [x1, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [x1, #1, mul vl]
; CHECK-NEXT: st1d { z1.d }, p0, [x1] ; CHECK-NEXT: st1d { z1.d }, p0, [x1]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
ret void ret void
} }
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