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llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Show First 20 Lines • Show All 270 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov w8, #2147483647 ; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: csel w19, w8, w19, gt ; CHECK-NEXT: csel w19, w8, w19, gt
; CHECK-NEXT: mov v1.16b, v0.16b ; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
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; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f) %x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x ret <1 x i32> %x
} }
define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) { define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-LABEL: test_signed_v2f128_v2i32: ; CHECK-LABEL: test_signed_v2f128_v2i32:
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; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: mov v0.s[1], w22 ; CHECK-NEXT: mov v0.s[1], w22
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: .cfi_adjust_cfa_offset 64
; CHECK-NEXT: .cfi_adjust_cfa_offset 64
; CHECK-NEXT: .cfi_adjust_cfa_offset 64
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) { define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-LABEL: test_signed_v3f128_v3i32: ; CHECK-LABEL: test_signed_v3f128_v3i32:
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; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: .cfi_adjust_cfa_offset 80
; CHECK-NEXT: .cfi_adjust_cfa_offset 80
; CHECK-NEXT: .cfi_adjust_cfa_offset 80
; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: add sp, sp, #128
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f) %x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) { define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-LABEL: test_signed_v4f128_v4i32: ; CHECK-LABEL: test_signed_v4f128_v4i32:
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; CHECK-NEXT: bl __unordtf2 ; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csel w8, wzr, w19, ne ; CHECK-NEXT: csel w8, wzr, w19, ne
; CHECK-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: .cfi_adjust_cfa_offset 96
; CHECK-NEXT: .cfi_adjust_cfa_offset 96
; CHECK-NEXT: .cfi_adjust_cfa_offset 96
; CHECK-NEXT: add sp, sp, #144 ; CHECK-NEXT: add sp, sp, #144
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
; ;
; FP16 to signed 32-bit -- Vector size variation ; FP16 to signed 32-bit -- Vector size variation
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float> %f) %x = call <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_signed_v2f32_v2i128(<2 x float> %f) { define <2 x i128> @test_signed_v2f32_v2i128(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i128: ; CHECK-LABEL: test_signed_v2f32_v2i128:
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float> %f) %x = call <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 2-Vector double to signed integer -- result size variation ; 2-Vector double to signed integer -- result size variation
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f) %x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f)
ret <2 x i100> %x ret <2 x i100> %x
} }
define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) { define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i128: ; CHECK-LABEL: test_signed_v2f64_v2i128:
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; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
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ReplyInline Actions

This is apparently incorrect.

MaskRay: This is apparently incorrect.
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f) %x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f)
ret <2 x i128> %x ret <2 x i128> %x
} }
; ;
; 4-Vector half to signed integer -- result size variation ; 4-Vector half to signed integer -- result size variation
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; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f) %x = call <4 x i100> @llvm.fptosi.sat.v4f16.v4i100(<4 x half> %f)
ret <4 x i100> %x ret <4 x i100> %x
} }
define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) { define <4 x i128> @test_signed_v4f16_v4i128(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i128: ; CHECK-LABEL: test_signed_v4f16_v4i128:
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; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x26, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr d10, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: csel x1, xzr, x8, vs ; CHECK-NEXT: csel x1, xzr, x8, vs
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f) %x = call <4 x i128> @llvm.fptosi.sat.v4f16.v4i128(<4 x half> %f)
ret <4 x i128> %x ret <4 x i128> %x
} }