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Differential D109253 Diff 370649 llvm/test/CodeGen/AArch64/addsub-constant-folding.ll

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llvm/test/CodeGen/AArch64/addsub-constant-folding.ll

Show All 22 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: add w0, w19, #10 ; CHECK-NEXT: add w0, w19, #10
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 28 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: add w0, w19, #6 ; CHECK-NEXT: add w0, w19, #6
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6 ; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 30 Lines
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8 ; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #-6 ; CHECK-NEXT: mov w8, #-6
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add i32 %arg, 8 %t0 = add i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_const_sub(<4 x i32> %arg) { define <4 x i32> @vec_add_const_const_sub(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: mvni v0.4s, #5 ; CHECK-NEXT: mvni v0.4s, #5
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 28 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: sub w0, w19, #6 ; CHECK-NEXT: sub w0, w19, #6
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: mvni v0.4s, #5 ; CHECK-NEXT: mvni v0.4s, #5
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 28 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: sub w0, w19, #10 ; CHECK-NEXT: sub w0, w19, #10
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 30 Lines
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8 ; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #10 ; CHECK-NEXT: mov w8, #10
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8 %t0 = sub i32 %arg, 8
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_const_sub(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_const_sub(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2 ; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 31 Lines
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w8, w0 ; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #10 ; CHECK-NEXT: mov w8, #10
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 8, %arg %t0 = sub i32 8, %arg
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_const_sub_add_const(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_add_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #10 ; CHECK-NEXT: movi v0.4s, #10
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 31 Lines
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w8, w0 ; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #6 ; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 8, %arg %t0 = sub i32 8, %arg
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_const_sub_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_sub_const(<4 x i32> %arg) {
Show All 17 Lines
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #6 ; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
Show All 30 Lines
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w8, #8 ; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: sub w19, w8, w0 ; CHECK-NEXT: sub w19, w8, w0
; CHECK-NEXT: mov w0, w19 ; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: mov w8, #2 ; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: sub w0, w8, w19 ; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_adjust_cfa_offset -16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub i32 8, %arg %t0 = sub i32 8, %arg
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) {
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; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl vec_use ; CHECK-NEXT: bl vec_use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2 ; CHECK-NEXT: movi v0.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: .cfi_adjust_cfa_offset 16
; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
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