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llvm/lib/Target/ARC/ARCInstrInfo.td
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| // Pattern generation for different instruction variants. | // Pattern generation for different instruction variants. | ||||
| multiclass MultiPat<SDPatternOperator InFrag, | multiclass MultiPat<SDPatternOperator InFrag, | ||||
| Instruction RRR, Instruction RRU6, Instruction RRLImm> { | Instruction RRR, Instruction RRU6, Instruction RRLImm> { | ||||
| def _rrr : Pat<(InFrag i32:$B, i32:$C), (RRR i32:$B, i32:$C)>; | def _rrr : Pat<(InFrag i32:$B, i32:$C), (RRR i32:$B, i32:$C)>; | ||||
| def _rru6 : Pat<(InFrag i32:$B, immU6:$U6), (RRU6 i32:$B, immU6:$U6)>; | def _rru6 : Pat<(InFrag i32:$B, immU6:$U6), (RRU6 i32:$B, immU6:$U6)>; | ||||
| def _rrlimm : Pat<(InFrag i32:$B, imm32:$LImm), (RRLImm i32:$B, imm32:$LImm)>; | def _rrlimm : Pat<(InFrag i32:$B, imm32:$LImm), (RRLImm i32:$B, imm32:$LImm)>; | ||||
| } | } | ||||
| // NOTE: This could be specialized later with a custom `PrintMethod` for | |||||
| // displaying the aux register name. E.g. `[%count0]` instead of [33]. | |||||
| def AuxReg : Operand<i32>; | |||||
| def LR_rs12 : F32_SOP_RS12<0b00100, 0b101010, 0, | |||||
| (outs GPR32:$B), (ins AuxReg:$C), | |||||
| "lr\t$B, [$C]", []>; | |||||
| def LR_ru6 : F32_SOP_RU6<0b00100, 0b101010, 0, | |||||
| (outs GPR32:$B), (ins AuxReg:$C), | |||||
| "lr\t$B, [$C]", []>; | |||||
| def: Pat<(i32 readcyclecounter), (LR_rs12 0x21) >; // read timer | |||||
| // --------------------------------------------------------------------------- | // --------------------------------------------------------------------------- | ||||
| // Instruction definitions and patterns for 3 operand binary instructions. | // Instruction definitions and patterns for 3 operand binary instructions. | ||||
| // --------------------------------------------------------------------------- | // --------------------------------------------------------------------------- | ||||
| // Definitions for 3 operand binary instructions. | // Definitions for 3 operand binary instructions. | ||||
| defm ADD : ArcBinaryGEN4Inst<0b000000, "add",1>; | defm ADD : ArcBinaryGEN4Inst<0b000000, "add",1>; | ||||
| defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">; | defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">; | ||||
| defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">; | defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">; | ||||
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