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Differential D108598 Diff 368421 llvm/lib/Target/ARC/ARCISelLowering.cpp

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llvm/lib/Target/ARC/ARCISelLowering.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines	case ISD::SETLE:
return ARCCC::LE;		return ARCCC::LE;
case ISD::SETNE:		case ISD::SETNE:
return ARCCC::NE;		return ARCCC::NE;
default:		default:
llvm_unreachable("Unhandled ISDCC code.");		llvm_unreachable("Unhandled ISDCC code.");
}		}
}		}

		void ARCTargetLowering::ReplaceNodeResults(SDNode *N,
		SmallVectorImpl<SDValue> &Results,
		SelectionDAG &DAG) const {
		LLVM_DEBUG(dbgs() << "[ARC-ISEL] ReplaceNodeResults ");
		LLVM_DEBUG(N->dump(&DAG));
		LLVM_DEBUG(dbgs() << "; use_count=" << N->use_size() << "\n");

		switch (N->getOpcode()) {
		case ISD::READCYCLECOUNTER:
		if (N->getValueType(0) == MVT::i64) {
		// We read the TIMER0 and zero-extend it to 64-bits as the intrinsic
		// requires.
		SDValue V =
		DAG.getNode(ISD::READCYCLECOUNTER, SDLoc(N),
		DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0));
		SDValue Op = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), MVT::i64, V);
		Results.push_back(Op);
		Results.push_back(V.getValue(1));
		}
		break;
		default:
		break;
		}
		}

ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,		ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
const ARCSubtarget &Subtarget)		const ARCSubtarget &Subtarget)
: TargetLowering(TM), Subtarget(Subtarget) {		: TargetLowering(TM), Subtarget(Subtarget) {
// Set up the register classes.		// Set up the register classes.
addRegisterClass(MVT::i32, &ARC::GPR32RegClass);		addRegisterClass(MVT::i32, &ARC::GPR32RegClass);

// Compute derived properties from the register classes		// Compute derived properties from the register classes
computeRegisterProperties(Subtarget.getRegisterInfo());		computeRegisterProperties(Subtarget.getRegisterInfo());
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,

// Sign extend inreg		// Sign extend inreg
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);		setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);

// TODO: Predicate these with `options.hasBitScan() ? Legal : Expand`		// TODO: Predicate these with `options.hasBitScan() ? Legal : Expand`
// when the HasBitScan predicate is available.		// when the HasBitScan predicate is available.
setOperationAction(ISD::CTLZ, MVT::i32, Legal);		setOperationAction(ISD::CTLZ, MVT::i32, Legal);
setOperationAction(ISD::CTTZ, MVT::i32, Legal);		setOperationAction(ISD::CTTZ, MVT::i32, Legal);

		setOperationAction(ISD::READCYCLECOUNTER, MVT::i32, Legal);
		setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
		isTypeLegal(MVT::i64) ? Legal : Custom);
}		}
		markslUnsubmitted Not Done Reply Inline Actions Please use setOperationAction(ISD::READCYCLECOUNTER,MVT::i64, isTypeLegal(MVT::i64)?Legal:Custom); marksl: Please use setOperationAction(ISD::READCYCLECOUNTER,MVT::i64…
		thomasjohnsAuthorUnsubmitted Done Reply Inline Actions Thanks, will do! thomasjohns: Thanks, will do!

const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {		const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {		switch (Opcode) {
case ARCISD::BL:		case ARCISD::BL:
return "ARCISD::BL";		return "ARCISD::BL";
case ARCISD::CMOV:		case ARCISD::CMOV:
return "ARCISD::CMOV";		return "ARCISD::CMOV";
case ARCISD::CMP:		case ARCISD::CMP:
▲ Show 20 Lines • Show All 609 Lines • ▼ Show 20 Lines	SDValue ARCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::BR_CC:		case ISD::BR_CC:
return LowerBR_CC(Op, DAG);		return LowerBR_CC(Op, DAG);
case ISD::SIGN_EXTEND_INREG:		case ISD::SIGN_EXTEND_INREG:
return LowerSIGN_EXTEND_INREG(Op, DAG);		return LowerSIGN_EXTEND_INREG(Op, DAG);
case ISD::JumpTable:		case ISD::JumpTable:
return LowerJumpTable(Op, DAG);		return LowerJumpTable(Op, DAG);
case ISD::VASTART:		case ISD::VASTART:
return LowerVASTART(Op, DAG);		return LowerVASTART(Op, DAG);
		case ISD::READCYCLECOUNTER:
		// As of LLVM 3.8, the lowering code insists that we customize it even
		// though we've declared the i32 version as legal. This is because it only
		// thinks i64 is the truly supported version. We've already converted the
		// i64 version to a widened i32.
		assert(Op.getSimpleValueType() == MVT::i32);
		return Op;
default:		default:
llvm_unreachable("unimplemented operand");		llvm_unreachable("unimplemented operand");
}		}
}		}