Differential D106033 Diff 362226 clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
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clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
| Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK1-NEXT: br label [[COND_END]] | // CHECK1-NEXT: br label [[COND_END]] | ||||
| // CHECK1: cond.end: | // CHECK1: cond.end: | ||||
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK1: omp.inner.for.cond: | // CHECK1: omp.inner.for.cond: | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK1-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
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| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 | // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
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| // CHECK1-NEXT: br label [[COND_END]] | // CHECK1-NEXT: br label [[COND_END]] | ||||
| // CHECK1: cond.end: | // CHECK1: cond.end: | ||||
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK1: omp.inner.for.cond: | // CHECK1: omp.inner.for.cond: | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK1-NEXT: store i32 [[ADD2]], i32* [[T_VAR]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
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| // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK2-NEXT: br label [[COND_END]] | // CHECK2-NEXT: br label [[COND_END]] | ||||
| // CHECK2: cond.end: | // CHECK2: cond.end: | ||||
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK2: omp.inner.for.cond: | // CHECK2: omp.inner.for.cond: | ||||
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK2: omp.inner.for.body: | // CHECK2: omp.inner.for.body: | ||||
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK2-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK2: omp.body.continue: | // CHECK2: omp.body.continue: | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK2: omp.inner.for.inc: | // CHECK2: omp.inner.for.inc: | ||||
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK2: omp.inner.for.end: | // CHECK2: omp.inner.for.end: | ||||
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK2: omp.loop.exit: | // CHECK2: omp.loop.exit: | ||||
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 | // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 | // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK2-NEXT: br label [[COND_END]] | // CHECK2-NEXT: br label [[COND_END]] | ||||
| // CHECK2: cond.end: | // CHECK2: cond.end: | ||||
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK2: omp.inner.for.cond: | // CHECK2: omp.inner.for.cond: | ||||
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK2: omp.inner.for.body: | // CHECK2: omp.inner.for.body: | ||||
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK2-NEXT: store i32 [[ADD2]], i32* [[T_VAR]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK2: omp.body.continue: | // CHECK2: omp.body.continue: | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK2: omp.inner.for.inc: | // CHECK2: omp.inner.for.inc: | ||||
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | ||||
| // CHECK2: omp.inner.for.end: | // CHECK2: omp.inner.for.end: | ||||
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK2: omp.loop.exit: | // CHECK2: omp.loop.exit: | ||||
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 | // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK3-NEXT: br label [[COND_END]] | // CHECK3-NEXT: br label [[COND_END]] | ||||
| // CHECK3: cond.end: | // CHECK3: cond.end: | ||||
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK3: omp.inner.for.cond: | // CHECK3: omp.inner.for.cond: | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK3-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK3: omp.loop.exit: | // CHECK3: omp.loop.exit: | ||||
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 | // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK3-NEXT: br label [[COND_END]] | // CHECK3-NEXT: br label [[COND_END]] | ||||
| // CHECK3: cond.end: | // CHECK3: cond.end: | ||||
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK3: omp.inner.for.cond: | // CHECK3: omp.inner.for.cond: | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK3-NEXT: store i32 [[ADD2]], i32* [[T_VAR]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK3: omp.loop.exit: | // CHECK3: omp.loop.exit: | ||||
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 | // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 | ||||
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 | // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK4-NEXT: br label [[COND_END]] | // CHECK4-NEXT: br label [[COND_END]] | ||||
| // CHECK4: cond.end: | // CHECK4: cond.end: | ||||
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK4: omp.inner.for.cond: | // CHECK4: omp.inner.for.cond: | ||||
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK4: omp.inner.for.body: | // CHECK4: omp.inner.for.body: | ||||
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK4-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK4: omp.body.continue: | // CHECK4: omp.body.continue: | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK4: omp.inner.for.inc: | // CHECK4: omp.inner.for.inc: | ||||
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | ||||
| // CHECK4: omp.inner.for.end: | // CHECK4: omp.inner.for.end: | ||||
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK4: omp.loop.exit: | // CHECK4: omp.loop.exit: | ||||
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 | // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 | ||||
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 | // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 24 Lines | |||||
| // CHECK4-NEXT: br label [[COND_END]] | // CHECK4-NEXT: br label [[COND_END]] | ||||
| // CHECK4: cond.end: | // CHECK4: cond.end: | ||||
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK4: omp.inner.for.cond: | // CHECK4: omp.inner.for.cond: | ||||
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK4: omp.inner.for.body: | // CHECK4: omp.inner.for.body: | ||||
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK4-NEXT: store i32 [[ADD2]], i32* [[T_VAR]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK4: omp.body.continue: | // CHECK4: omp.body.continue: | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK4: omp.inner.for.inc: | // CHECK4: omp.inner.for.inc: | ||||
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 | ||||
| // CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | ||||
| // CHECK4: omp.inner.for.end: | // CHECK4: omp.inner.for.end: | ||||
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK4: omp.loop.exit: | // CHECK4: omp.loop.exit: | ||||
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 | ||||
| // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 473 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 25 Lines | |||||
| // CHECK9-NEXT: br label [[COND_END]] | // CHECK9-NEXT: br label [[COND_END]] | ||||
| // CHECK9: cond.end: | // CHECK9: cond.end: | ||||
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK9: omp.inner.for.cond: | // CHECK9: omp.inner.for.cond: | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK9-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP13]], align 8, !llvm.access.group !4 | // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 | // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 | ||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 | // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 | // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| ▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines | |||||
| // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 | ||||
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) | ||||
| // CHECK10-NEXT: ret void | // CHECK10-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK10-NEXT: entry: | // CHECK10-NEXT: entry: | ||||
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 25 Lines | |||||
| // CHECK10-NEXT: br label [[COND_END]] | // CHECK10-NEXT: br label [[COND_END]] | ||||
| // CHECK10: cond.end: | // CHECK10: cond.end: | ||||
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK10: omp.inner.for.cond: | // CHECK10: omp.inner.for.cond: | ||||
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK10: omp.inner.for.body: | // CHECK10: omp.inner.for.body: | ||||
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 | // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] | // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] | ||||
| // CHECK10-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 | // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 | ||||
| // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP13]], align 8, !llvm.access.group !4 | // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 | // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 | ||||
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK10: omp.body.continue: | // CHECK10: omp.body.continue: | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK10: omp.inner.for.inc: | // CHECK10: omp.inner.for.inc: | ||||
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 | // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 | ||||
| // CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | ||||
| // CHECK10: omp.inner.for.end: | // CHECK10: omp.inner.for.end: | ||||
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK10: omp.loop.exit: | // CHECK10: omp.loop.exit: | ||||
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 | // CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 | ||||
| // CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
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