Differential D106033 Diff 362226 clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
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clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
| Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | ||||
| // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 | // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK1-NEXT: br label [[COND_END]] | // CHECK1-NEXT: br label [[COND_END]] | ||||
| // CHECK1: cond.end: | // CHECK1: cond.end: | ||||
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK1: omp.inner.for.cond: | // CHECK1: omp.inner.for.cond: | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 | // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 | // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 | ||||
| // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | ||||
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP2]], i32 0, i32 0 | // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 | // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 | ||||
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] | // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] | ||||
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 | // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 | ||||
| // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | ||||
| // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | ||||
| // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 | // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 | // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK2-NEXT: br label [[COND_END]] | // CHECK2-NEXT: br label [[COND_END]] | ||||
| // CHECK2: cond.end: | // CHECK2: cond.end: | ||||
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK2: omp.inner.for.cond: | // CHECK2: omp.inner.for.cond: | ||||
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK2: omp.inner.for.body: | // CHECK2: omp.inner.for.body: | ||||
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 | // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 | ||||
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 | // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 | ||||
| // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | ||||
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP2]], i32 0, i32 0 | // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 | ||||
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 | // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 | ||||
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] | // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] | ||||
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 | // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 | ||||
| // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | ||||
| // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK2: omp.body.continue: | // CHECK2: omp.body.continue: | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK2: omp.inner.for.inc: | // CHECK2: omp.inner.for.inc: | ||||
| // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 | ||||
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] | ||||
| // CHECK2: omp.inner.for.end: | // CHECK2: omp.inner.for.end: | ||||
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK2: omp.loop.exit: | // CHECK2: omp.loop.exit: | ||||
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | ||||
| // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 | // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK3-NEXT: br label [[COND_END]] | // CHECK3-NEXT: br label [[COND_END]] | ||||
| // CHECK3: cond.end: | // CHECK3: cond.end: | ||||
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK3: omp.inner.for.cond: | // CHECK3: omp.inner.for.cond: | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 | // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 | // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 | ||||
| // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | ||||
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP2]], i32 0, i32 0 | // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] | // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] | ||||
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] | // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] | ||||
| // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK3: omp.loop.exit: | // CHECK3: omp.loop.exit: | ||||
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | ||||
| // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 | // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 | ||||
| // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 | // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK4-NEXT: br label [[COND_END]] | // CHECK4-NEXT: br label [[COND_END]] | ||||
| // CHECK4: cond.end: | // CHECK4: cond.end: | ||||
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK4: omp.inner.for.cond: | // CHECK4: omp.inner.for.cond: | ||||
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK4: omp.inner.for.body: | // CHECK4: omp.inner.for.body: | ||||
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 | // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 | ||||
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 | // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 | ||||
| // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 | ||||
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP2]], i32 0, i32 0 | // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 | ||||
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] | // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] | ||||
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] | // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] | ||||
| // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK4: omp.body.continue: | // CHECK4: omp.body.continue: | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK4: omp.inner.for.inc: | // CHECK4: omp.inner.for.inc: | ||||
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 | ||||
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK4: omp.inner.for.end: | // CHECK4: omp.inner.for.end: | ||||
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK4: omp.loop.exit: | // CHECK4: omp.loop.exit: | ||||
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 455 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* | // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* | ||||
| // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 | // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 | ||||
| // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 | // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 | ||||
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) | // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | ||||
| ▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: br label [[COND_END]] | // CHECK9-NEXT: br label [[COND_END]] | ||||
| // CHECK9: cond.end: | // CHECK9: cond.end: | ||||
| // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | ||||
| // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK9: omp.inner.for.cond: | // CHECK9: omp.inner.for.cond: | ||||
| // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[CMP12:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] | // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] | ||||
| // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP28]], 0 | // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 | ||||
| // CHECK9-NEXT: [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1 | // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 | ||||
| // CHECK9-NEXT: [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]] | // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] | ||||
| // CHECK9-NEXT: [[CONV16:%.*]] = sext i32 [[MUL15]] to i64 | // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 | ||||
| // CHECK9-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP27]], [[CONV16]] | // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] | ||||
| // CHECK9-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 1 | // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL18]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] | ||||
| // CHECK9-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD]] to i32 | // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 | ||||
| // CHECK9-NEXT: store i32 [[CONV19]], i32* [[I9]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[SUB20:%.*]] = sub nsw i32 [[TMP31]], 0 | // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 | ||||
| // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i32 [[SUB20]], 1 | // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 | ||||
| // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i32 1, [[DIV21]] | // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] | ||||
| // CHECK9-NEXT: [[CONV23:%.*]] = sext i32 [[MUL22]] to i64 | // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 | ||||
| // CHECK9-NEXT: [[DIV24:%.*]] = sdiv i64 [[TMP30]], [[CONV23]] | // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] | ||||
| // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP32]], 0 | // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 | ||||
| // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 | // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 | ||||
| // CHECK9-NEXT: [[MUL27:%.*]] = mul nsw i32 1, [[DIV26]] | // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] | ||||
| // CHECK9-NEXT: [[CONV28:%.*]] = sext i32 [[MUL27]] to i64 | // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 | ||||
| // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i64 [[DIV24]], [[CONV28]] | // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] | ||||
| // CHECK9-NEXT: [[SUB30:%.*]] = sub nsw i64 [[TMP29]], [[MUL29]] | // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] | ||||
| // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[SUB30]], 1 | // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 | ||||
| // CHECK9-NEXT: [[ADD32:%.*]] = add nsw i64 0, [[MUL31]] | // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] | ||||
| // CHECK9-NEXT: [[CONV33:%.*]] = trunc i64 [[ADD32]] to i32 | // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 | ||||
| // CHECK9-NEXT: store i32 [[CONV33]], i32* [[J10]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP33]] to i64 | // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 | ||||
| // CHECK9-NEXT: [[TMP34:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP8]] | // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] | ||||
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i64 [[TMP34]] | // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] | ||||
| // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP35]] to i64 | // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 | ||||
| // CHECK9-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM34]] | // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] | ||||
| // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX35]], align 4, !llvm.access.group !5 | // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 [[TMP36]], 1 | // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 | ||||
| // CHECK9-NEXT: store i64 [[ADD36]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | ||||
| // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| ▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | ||||
| // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 | // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 | // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 | ||||
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | ||||
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK9-NEXT: br label [[COND_END]] | // CHECK9-NEXT: br label [[COND_END]] | ||||
| // CHECK9: cond.end: | // CHECK9: cond.end: | ||||
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK9: omp.inner.for.cond: | // CHECK9: omp.inner.for.cond: | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 | // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 | // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 | ||||
| // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | ||||
| // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 | // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 | ||||
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP2]], i64 0, i64 [[IDXPROM]] | // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] | ||||
| // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 | // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 | ||||
| // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | ||||
| // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines | |||||
| // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* | // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* | ||||
| // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 | // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 | ||||
| // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 | // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 | ||||
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) | // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) | ||||
| // CHECK10-NEXT: ret void | // CHECK10-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK10-NEXT: entry: | // CHECK10-NEXT: entry: | ||||
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 | // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 | // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | ||||
| ▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | |||||
| // CHECK10-NEXT: br label [[COND_END]] | // CHECK10-NEXT: br label [[COND_END]] | ||||
| // CHECK10: cond.end: | // CHECK10: cond.end: | ||||
| // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | ||||
| // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK10: omp.inner.for.cond: | // CHECK10: omp.inner.for.cond: | ||||
| // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[CMP12:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] | // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] | ||||
| // CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK10: omp.inner.for.body: | // CHECK10: omp.inner.for.body: | ||||
| // CHECK10-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP28]], 0 | // CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 | ||||
| // CHECK10-NEXT: [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1 | // CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 | ||||
| // CHECK10-NEXT: [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]] | // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] | ||||
| // CHECK10-NEXT: [[CONV16:%.*]] = sext i32 [[MUL15]] to i64 | // CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 | ||||
| // CHECK10-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP27]], [[CONV16]] | // CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] | ||||
| // CHECK10-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 1 | // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 | ||||
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL18]] | // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] | ||||
| // CHECK10-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD]] to i32 | // CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 | ||||
| // CHECK10-NEXT: store i32 [[CONV19]], i32* [[I9]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[SUB20:%.*]] = sub nsw i32 [[TMP31]], 0 | // CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 | ||||
| // CHECK10-NEXT: [[DIV21:%.*]] = sdiv i32 [[SUB20]], 1 | // CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 | ||||
| // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i32 1, [[DIV21]] | // CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] | ||||
| // CHECK10-NEXT: [[CONV23:%.*]] = sext i32 [[MUL22]] to i64 | // CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 | ||||
| // CHECK10-NEXT: [[DIV24:%.*]] = sdiv i64 [[TMP30]], [[CONV23]] | // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] | ||||
| // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP32]], 0 | // CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 | ||||
| // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 | // CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 | ||||
| // CHECK10-NEXT: [[MUL27:%.*]] = mul nsw i32 1, [[DIV26]] | // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] | ||||
| // CHECK10-NEXT: [[CONV28:%.*]] = sext i32 [[MUL27]] to i64 | // CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 | ||||
| // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i64 [[DIV24]], [[CONV28]] | // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] | ||||
| // CHECK10-NEXT: [[SUB30:%.*]] = sub nsw i64 [[TMP29]], [[MUL29]] | // CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] | ||||
| // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[SUB30]], 1 | // CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 | ||||
| // CHECK10-NEXT: [[ADD32:%.*]] = add nsw i64 0, [[MUL31]] | // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] | ||||
| // CHECK10-NEXT: [[CONV33:%.*]] = trunc i64 [[ADD32]] to i32 | // CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 | ||||
| // CHECK10-NEXT: store i32 [[CONV33]], i32* [[J10]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP33]] to i64 | // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 | ||||
| // CHECK10-NEXT: [[TMP34:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP8]] | // CHECK10-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] | ||||
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i64 [[TMP34]] | // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] | ||||
| // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP35]] to i64 | // CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 | ||||
| // CHECK10-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM34]] | // CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] | ||||
| // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX35]], align 4, !llvm.access.group !5 | // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK10: omp.body.continue: | // CHECK10: omp.body.continue: | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK10: omp.inner.for.inc: | // CHECK10: omp.inner.for.inc: | ||||
| // CHECK10-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 [[TMP36]], 1 | // CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 | ||||
| // CHECK10-NEXT: store i64 [[ADD36]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | // CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] | ||||
| // CHECK10: omp.inner.for.end: | // CHECK10: omp.inner.for.end: | ||||
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK10: omp.loop.exit: | // CHECK10: omp.loop.exit: | ||||
| // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | ||||
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | ||||
| // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| ▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | |||||
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | ||||
| // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 | // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 | ||||
| // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 | // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 | ||||
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | ||||
| // CHECK10-NEXT: ret void | // CHECK10-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK10-NEXT: entry: | // CHECK10-NEXT: entry: | ||||
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 | ||||
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK10-NEXT: br label [[COND_END]] | // CHECK10-NEXT: br label [[COND_END]] | ||||
| // CHECK10: cond.end: | // CHECK10: cond.end: | ||||
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK10: omp.inner.for.cond: | // CHECK10: omp.inner.for.cond: | ||||
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK10: omp.inner.for.body: | // CHECK10: omp.inner.for.body: | ||||
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 | // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 | ||||
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 | // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 | ||||
| // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | ||||
| // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 | // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 | ||||
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP2]], i64 0, i64 [[IDXPROM]] | // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] | ||||
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 | // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 | ||||
| // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] | ||||
| // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK10: omp.body.continue: | // CHECK10: omp.body.continue: | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK10: omp.inner.for.inc: | // CHECK10: omp.inner.for.inc: | ||||
| // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 | ||||
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] | ||||
| // CHECK10: omp.inner.for.end: | // CHECK10: omp.inner.for.end: | ||||
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK10: omp.loop.exit: | // CHECK10: omp.loop.exit: | ||||
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines | |||||
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 | // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 | ||||
| // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 | // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 | ||||
| // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 | // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 | ||||
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) | // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) | ||||
| // CHECK11-NEXT: ret void | // CHECK11-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK11-NEXT: entry: | // CHECK11-NEXT: entry: | ||||
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| ▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines | |||||
| // CHECK11-NEXT: br label [[COND_END]] | // CHECK11-NEXT: br label [[COND_END]] | ||||
| // CHECK11: cond.end: | // CHECK11: cond.end: | ||||
| // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | ||||
| // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK11: omp.inner.for.cond: | // CHECK11: omp.inner.for.cond: | ||||
| // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[CMP12:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] | // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] | ||||
| // CHECK11-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK11: omp.inner.for.body: | // CHECK11: omp.inner.for.body: | ||||
| // CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP28]], 0 | // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 | ||||
| // CHECK11-NEXT: [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1 | // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 | ||||
| // CHECK11-NEXT: [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]] | // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] | ||||
| // CHECK11-NEXT: [[CONV16:%.*]] = sext i32 [[MUL15]] to i64 | // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 | ||||
| // CHECK11-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP27]], [[CONV16]] | // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] | ||||
| // CHECK11-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 1 | // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 | ||||
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL18]] | // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] | ||||
| // CHECK11-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD]] to i32 | // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 | ||||
| // CHECK11-NEXT: store i32 [[CONV19]], i32* [[I9]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[SUB20:%.*]] = sub nsw i32 [[TMP31]], 0 | // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 | ||||
| // CHECK11-NEXT: [[DIV21:%.*]] = sdiv i32 [[SUB20]], 1 | // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 | ||||
| // CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i32 1, [[DIV21]] | // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] | ||||
| // CHECK11-NEXT: [[CONV23:%.*]] = sext i32 [[MUL22]] to i64 | // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 | ||||
| // CHECK11-NEXT: [[DIV24:%.*]] = sdiv i64 [[TMP30]], [[CONV23]] | // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] | ||||
| // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP32]], 0 | // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 | ||||
| // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 | // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 | ||||
| // CHECK11-NEXT: [[MUL27:%.*]] = mul nsw i32 1, [[DIV26]] | // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] | ||||
| // CHECK11-NEXT: [[CONV28:%.*]] = sext i32 [[MUL27]] to i64 | // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 | ||||
| // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i64 [[DIV24]], [[CONV28]] | // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] | ||||
| // CHECK11-NEXT: [[SUB30:%.*]] = sub nsw i64 [[TMP29]], [[MUL29]] | // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] | ||||
| // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[SUB30]], 1 | // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 | ||||
| // CHECK11-NEXT: [[ADD32:%.*]] = add nsw i64 0, [[MUL31]] | // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] | ||||
| // CHECK11-NEXT: [[CONV33:%.*]] = trunc i64 [[ADD32]] to i32 | // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 | ||||
| // CHECK11-NEXT: store i32 [[CONV33]], i32* [[J10]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[TMP34:%.*]] = mul nsw i32 [[TMP33]], [[TMP8]] | // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] | ||||
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 [[TMP34]] | // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] | ||||
| // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP35]] | // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] | ||||
| // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !6 | // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK11: omp.body.continue: | // CHECK11: omp.body.continue: | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK11: omp.inner.for.inc: | // CHECK11: omp.inner.for.inc: | ||||
| // CHECK11-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP36]], 1 | // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 | ||||
| // CHECK11-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | ||||
| // CHECK11: omp.inner.for.end: | // CHECK11: omp.inner.for.end: | ||||
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK11: omp.loop.exit: | // CHECK11: omp.loop.exit: | ||||
| // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | ||||
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | ||||
| // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| ▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | |||||
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | ||||
| // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 | // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 | ||||
| // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 | // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 | ||||
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | ||||
| // CHECK11-NEXT: ret void | // CHECK11-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK11-NEXT: entry: | // CHECK11-NEXT: entry: | ||||
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | ||||
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| Show All 23 Lines | |||||
| // CHECK11-NEXT: br label [[COND_END]] | // CHECK11-NEXT: br label [[COND_END]] | ||||
| // CHECK11: cond.end: | // CHECK11: cond.end: | ||||
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK11: omp.inner.for.cond: | // CHECK11: omp.inner.for.cond: | ||||
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK11: omp.inner.for.body: | // CHECK11: omp.inner.for.body: | ||||
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 | // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 | ||||
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 | // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 | ||||
| // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | ||||
| // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP2]], i32 0, i32 [[TMP13]] | // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] | ||||
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] | // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] | ||||
| // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK11: omp.body.continue: | // CHECK11: omp.body.continue: | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK11: omp.inner.for.inc: | // CHECK11: omp.inner.for.inc: | ||||
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | ||||
| // CHECK11: omp.inner.for.end: | // CHECK11: omp.inner.for.end: | ||||
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK11: omp.loop.exit: | // CHECK11: omp.loop.exit: | ||||
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
| ▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines | |||||
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 | // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 | ||||
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 | // CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 | ||||
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 | // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 | ||||
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) | // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) | ||||
| // CHECK12-NEXT: ret void | // CHECK12-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK12-NEXT: entry: | // CHECK12-NEXT: entry: | ||||
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| ▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines | |||||
| // CHECK12-NEXT: br label [[COND_END]] | // CHECK12-NEXT: br label [[COND_END]] | ||||
| // CHECK12: cond.end: | // CHECK12: cond.end: | ||||
| // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] | ||||
| // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK12: omp.inner.for.cond: | // CHECK12: omp.inner.for.cond: | ||||
| // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[CMP12:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] | // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] | ||||
| // CHECK12-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK12: omp.inner.for.body: | // CHECK12: omp.inner.for.body: | ||||
| // CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[TMP28]], 0 | // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 | ||||
| // CHECK12-NEXT: [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1 | // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 | ||||
| // CHECK12-NEXT: [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]] | // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] | ||||
| // CHECK12-NEXT: [[CONV16:%.*]] = sext i32 [[MUL15]] to i64 | // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 | ||||
| // CHECK12-NEXT: [[DIV17:%.*]] = sdiv i64 [[TMP27]], [[CONV16]] | // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] | ||||
| // CHECK12-NEXT: [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 1 | // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 | ||||
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL18]] | // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] | ||||
| // CHECK12-NEXT: [[CONV19:%.*]] = trunc i64 [[ADD]] to i32 | // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 | ||||
| // CHECK12-NEXT: store i32 [[CONV19]], i32* [[I9]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[SUB20:%.*]] = sub nsw i32 [[TMP31]], 0 | // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 | ||||
| // CHECK12-NEXT: [[DIV21:%.*]] = sdiv i32 [[SUB20]], 1 | // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 | ||||
| // CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i32 1, [[DIV21]] | // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] | ||||
| // CHECK12-NEXT: [[CONV23:%.*]] = sext i32 [[MUL22]] to i64 | // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 | ||||
| // CHECK12-NEXT: [[DIV24:%.*]] = sdiv i64 [[TMP30]], [[CONV23]] | // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] | ||||
| // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP32]], 0 | // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 | ||||
| // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1 | // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 | ||||
| // CHECK12-NEXT: [[MUL27:%.*]] = mul nsw i32 1, [[DIV26]] | // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] | ||||
| // CHECK12-NEXT: [[CONV28:%.*]] = sext i32 [[MUL27]] to i64 | // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 | ||||
| // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i64 [[DIV24]], [[CONV28]] | // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] | ||||
| // CHECK12-NEXT: [[SUB30:%.*]] = sub nsw i64 [[TMP29]], [[MUL29]] | // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] | ||||
| // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[SUB30]], 1 | // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 | ||||
| // CHECK12-NEXT: [[ADD32:%.*]] = add nsw i64 0, [[MUL31]] | // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] | ||||
| // CHECK12-NEXT: [[CONV33:%.*]] = trunc i64 [[ADD32]] to i32 | // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 | ||||
| // CHECK12-NEXT: store i32 [[CONV33]], i32* [[J10]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[TMP34:%.*]] = mul nsw i32 [[TMP33]], [[TMP8]] | // CHECK12-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] | ||||
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 [[TMP34]] | // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] | ||||
| // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP35]] | // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] | ||||
| // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !6 | // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK12: omp.body.continue: | // CHECK12: omp.body.continue: | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK12: omp.inner.for.inc: | // CHECK12: omp.inner.for.inc: | ||||
| // CHECK12-NEXT: [[TMP36:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP36]], 1 | // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 | ||||
| // CHECK12-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] | ||||
| // CHECK12: omp.inner.for.end: | // CHECK12: omp.inner.for.end: | ||||
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK12: omp.loop.exit: | // CHECK12: omp.loop.exit: | ||||
| // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 | ||||
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) | ||||
| // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
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| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | ||||
| // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 | // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 | ||||
| // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 | // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 | ||||
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) | ||||
| // CHECK12-NEXT: ret void | // CHECK12-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK12-NEXT: entry: | // CHECK12-NEXT: entry: | ||||
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 | ||||
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
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| // CHECK12-NEXT: br label [[COND_END]] | // CHECK12-NEXT: br label [[COND_END]] | ||||
| // CHECK12: cond.end: | // CHECK12: cond.end: | ||||
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] | ||||
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 | ||||
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 | ||||
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK12: omp.inner.for.cond: | // CHECK12: omp.inner.for.cond: | ||||
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] | // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK12: omp.inner.for.body: | // CHECK12: omp.inner.for.body: | ||||
| // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 | // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 | ||||
| // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 | ||||
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 | // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 | ||||
| // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 | ||||
| // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] | ||||
| // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 | ||||
| // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] | ||||
| // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP2]], i32 0, i32 [[TMP13]] | // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] | ||||
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] | // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] | ||||
| // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK12: omp.body.continue: | // CHECK12: omp.body.continue: | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK12: omp.inner.for.inc: | // CHECK12: omp.inner.for.inc: | ||||
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 | // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 | ||||
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] | ||||
| // CHECK12: omp.inner.for.end: | // CHECK12: omp.inner.for.end: | ||||
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK12: omp.loop.exit: | // CHECK12: omp.loop.exit: | ||||
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) | ||||
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | // CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 | ||||
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