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clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
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| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
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| // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | ||||
| // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | ||||
| // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | ||||
| // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | ||||
| // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK1: omp_offload.failed.i: | // CHECK1: omp_offload.failed.i: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK1: .omp_outlined..1.exit: | // CHECK1: .omp_outlined..1.exit: | ||||
| // CHECK1-NEXT: ret i32 0 | // CHECK1-NEXT: ret i32 0 | ||||
| // | // | ||||
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| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | ||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
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| // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
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| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
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| // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
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| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | ||||
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 33 Lines | |||||
| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 381 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | ||||
| // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | ||||
| // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | ||||
| // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | ||||
| // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK2: omp_offload.failed.i: | // CHECK2: omp_offload.failed.i: | ||||
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK2: .omp_outlined..1.exit: | // CHECK2: .omp_outlined..1.exit: | ||||
| // CHECK2-NEXT: ret i32 0 | // CHECK2-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 15 Lines | |||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | ||||
| // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | // CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | ||||
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 33 Lines | |||||
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 371 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | ||||
| // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | ||||
| // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | ||||
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK3: omp_offload.failed.i: | // CHECK3: omp_offload.failed.i: | ||||
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK3: .omp_outlined..1.exit: | // CHECK3: .omp_outlined..1.exit: | ||||
| // CHECK3-NEXT: ret i32 0 | // CHECK3-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 10 Lines | |||||
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 454 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines | |||||
| // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 30 Lines | |||||
| // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 370 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | ||||
| // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | ||||
| // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | ||||
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK4: omp_offload.failed.i: | // CHECK4: omp_offload.failed.i: | ||||
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK4: .omp_outlined..1.exit: | // CHECK4: .omp_outlined..1.exit: | ||||
| // CHECK4-NEXT: ret i32 0 | // CHECK4-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 10 Lines | |||||
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 454 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | ||||
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | ||||
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines | |||||
| // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 30 Lines | |||||
| // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 380 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | ||||
| // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | ||||
| // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | ||||
| // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | ||||
| // CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK5: omp_offload.failed.i: | // CHECK5: omp_offload.failed.i: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK5: .omp_outlined..1.exit: | // CHECK5: .omp_outlined..1.exit: | ||||
| // CHECK5-NEXT: ret i32 0 | // CHECK5-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 15 Lines | |||||
| // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | ||||
| // CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | // CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | ||||
| // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 504 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK5: omp_if.then: | // CHECK5: omp_if.then: | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | ||||
| // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK5: omp_if.else: | // CHECK5: omp_if.else: | ||||
| // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK5-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR4]] | // CHECK5-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] | ||||
| // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK5-NEXT: br label [[OMP_IF_END]] | // CHECK5-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK5: omp_if.end: | // CHECK5: omp_if.end: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 33 Lines | |||||
| // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.9* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 381 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK6-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK6-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) | ||||
| // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) | ||||
| // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) | ||||
| // CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | // CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 | ||||
| // CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | // CHECK6-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 | ||||
| // CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK6-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK6-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK6-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK6: omp_offload.failed.i: | // CHECK6: omp_offload.failed.i: | ||||
| // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK6: .omp_outlined..1.exit: | // CHECK6: .omp_outlined..1.exit: | ||||
| // CHECK6-NEXT: ret i32 0 | // CHECK6-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 15 Lines | |||||
| // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 | ||||
| // CHECK6-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | // CHECK6-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 | ||||
| // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK6-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK6-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK6-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 504 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK6: omp_if.then: | // CHECK6: omp_if.then: | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | ||||
| // CHECK6-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK6-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK6: omp_if.else: | // CHECK6: omp_if.else: | ||||
| // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK6-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR4]] | // CHECK6-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] | ||||
| // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK6-NEXT: br label [[OMP_IF_END]] | // CHECK6-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK6: omp_if.end: | // CHECK6: omp_if.end: | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines | |||||
| // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 33 Lines | |||||
| // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.9* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 371 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | ||||
| // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | ||||
| // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | ||||
| // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK7-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK7-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK7: omp_offload.failed.i: | // CHECK7: omp_offload.failed.i: | ||||
| // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK7: .omp_outlined..1.exit: | // CHECK7: .omp_outlined..1.exit: | ||||
| // CHECK7-NEXT: ret i32 0 | // CHECK7-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 10 Lines | |||||
| // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 497 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK7: omp_if.then: | // CHECK7: omp_if.then: | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | ||||
| // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK7: omp_if.else: | // CHECK7: omp_if.else: | ||||
| // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK7-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR4]] | // CHECK7-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] | ||||
| // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK7-NEXT: br label [[OMP_IF_END]] | // CHECK7-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK7: omp_if.end: | // CHECK7: omp_if.end: | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines | |||||
| // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 30 Lines | |||||
| // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK7-NEXT: ret void | // CHECK7-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK7-NEXT: entry: | // CHECK7-NEXT: entry: | ||||
| // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 370 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK8-SAME: () #[[ATTR2:[0-9]+]] { | // CHECK8-SAME: () #[[ATTR2:[0-9]+]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR3:[0-9]+]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) | ||||
| // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) | ||||
| // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | // CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) | ||||
| // CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: [[TMP10:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | // CHECK8-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 | ||||
| // CHECK8-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR4]] | // CHECK8-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] | ||||
| // CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK8-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK8-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | // CHECK8-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] | ||||
| // CHECK8: omp_offload.failed.i: | // CHECK8: omp_offload.failed.i: | ||||
| // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] | ||||
| // CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | // CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] | ||||
| // CHECK8: .omp_outlined..1.exit: | // CHECK8: .omp_outlined..1.exit: | ||||
| // CHECK8-NEXT: ret i32 0 | // CHECK8-NEXT: ret i32 0 | ||||
| // | // | ||||
| Show All 10 Lines | |||||
| // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | // CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | // CHECK8-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | // CHECK8-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK8-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK8-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK8-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 497 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK8: omp_if.then: | // CHECK8: omp_if.then: | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | ||||
| // CHECK8-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK8-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK8: omp_if.else: | // CHECK8: omp_if.else: | ||||
| // CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK8-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK8-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR4]] | // CHECK8-NEXT: call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] | ||||
| // CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK8-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK8-NEXT: br label [[OMP_IF_END]] | // CHECK8-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK8: omp_if.end: | // CHECK8: omp_if.end: | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines | |||||
| // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 30 Lines | |||||
| // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK8-NEXT: ret void | // CHECK8-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 | // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 | ||||
| // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.8* noalias [[__CONTEXT:%.*]]) #[[ATTR3]] { | // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { | ||||
| // CHECK8-NEXT: entry: | // CHECK8-NEXT: entry: | ||||
| // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK8-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 4,180 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK17-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 | ||||
| // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 | ||||
| // CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 | ||||
| // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* | ||||
| // CHECK17-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* | ||||
| // CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* | ||||
| // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 | ||||
| // CHECK17-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 | ||||
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 | ||||
| // CHECK17-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 34 Lines | |||||
| // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | ||||
| // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | ||||
| // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | |||||
| // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK17-NEXT: ret void | // CHECK17-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK17-NEXT: entry: | // CHECK17-NEXT: entry: | ||||
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK18-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 | ||||
| // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 | ||||
| // CHECK18-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 | ||||
| // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* | ||||
| // CHECK18-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* | ||||
| // CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* | ||||
| // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 | ||||
| // CHECK18-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 | ||||
| // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 | ||||
| // CHECK18-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 34 Lines | |||||
| // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* | ||||
| // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 | ||||
| // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | |||||
| // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK18-NEXT: ret void | // CHECK18-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK18-NEXT: entry: | // CHECK18-NEXT: entry: | ||||
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK19-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 | ||||
| // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 | ||||
| // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* | ||||
| // CHECK19-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK19-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 | ||||
| // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | |||||
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | |||||
| // CHECK19-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK19-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 31 Lines | |||||
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | ||||
| // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | ||||
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines | |||||
| // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK19-NEXT: ret void | // CHECK19-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK19-NEXT: entry: | // CHECK19-NEXT: entry: | ||||
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK20-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 | ||||
| // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 | ||||
| // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* | ||||
| // CHECK20-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK20-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 | ||||
| // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | |||||
| // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | |||||
| // CHECK20-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK20-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| Show All 31 Lines | |||||
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 | ||||
| // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 | ||||
| // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines | |||||
| // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK20-NEXT: ret void | // CHECK20-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK20-NEXT: entry: | // CHECK20-NEXT: entry: | ||||
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[A5:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[A5:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK21-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 | ||||
| // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 | ||||
| // CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 | ||||
| // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* | ||||
| // CHECK21-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* | ||||
| // CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* | ||||
| // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 | ||||
| // CHECK21-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 | ||||
| // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 | ||||
| // CHECK21-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK21: omp_if.then: | // CHECK21: omp_if.then: | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | ||||
| // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK21: omp_if.else: | // CHECK21: omp_if.else: | ||||
| // CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK21-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR2:[0-9]+]] | // CHECK21-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] | ||||
| // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK21-NEXT: br label [[OMP_IF_END]] | // CHECK21-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK21: omp_if.end: | // CHECK21: omp_if.end: | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines | |||||
| // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK21-NEXT: ret void | // CHECK21-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK21-NEXT: entry: | // CHECK21-NEXT: entry: | ||||
| // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* | ||||
| // CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | // CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 | ||||
| // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | // CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[LIN4:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[A5:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[A5:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK22-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 | ||||
| // CHECK22-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 | // CHECK22-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 | ||||
| // CHECK22-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 | ||||
| // CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* | ||||
| // CHECK22-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* | ||||
| // CHECK22-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* | ||||
| // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8 | ||||
| // CHECK22-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK22-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 | ||||
| // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | // CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 | ||||
| // CHECK22-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | // CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 | ||||
| // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK22-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK22-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | // CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* | ||||
| // CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | // CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 | ||||
| // CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 | ||||
| // CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | // CHECK22-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 | ||||
| // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 | ||||
| ▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | // CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* | ||||
| // CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | // CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 | ||||
| // CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | // CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK22: omp_if.then: | // CHECK22: omp_if.then: | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) | ||||
| // CHECK22-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK22-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK22: omp_if.else: | // CHECK22: omp_if.else: | ||||
| // CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK22-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK22-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR2:[0-9]+]] | // CHECK22-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] | ||||
| // CHECK22-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK22-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK22-NEXT: br label [[OMP_IF_END]] | // CHECK22-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK22: omp_if.end: | // CHECK22: omp_if.end: | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 | ||||
| // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 | ||||
| ▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines | |||||
| // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | // CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* | ||||
| // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | // CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 | ||||
| // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | // CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 | ||||
| // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK22-NEXT: ret void | // CHECK22-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK22-NEXT: entry: | // CHECK22-NEXT: entry: | ||||
| // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 | // CHECK22-NEXT: [[TMP:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK23-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 | ||||
| // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 | ||||
| // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* | ||||
| // CHECK23-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK23-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 | ||||
| // CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | |||||
| // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | |||||
| // CHECK23-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK23-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK23: omp_if.then: | // CHECK23: omp_if.then: | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | ||||
| // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK23: omp_if.else: | // CHECK23: omp_if.else: | ||||
| // CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK23-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) #[[ATTR2:[0-9]+]] | // CHECK23-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] | ||||
| // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK23-NEXT: br label [[OMP_IF_END]] | // CHECK23-NEXT: br label [[OMP_IF_END]] | ||||
| // CHECK23: omp_if.end: | // CHECK23: omp_if.end: | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 | ||||
| // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 | ||||
| ▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | |||||
| // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 | ||||
| // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK23-NEXT: ret void | // CHECK23-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 | // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 | ||||
| // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK23-NEXT: entry: | // CHECK23-NEXT: entry: | ||||
| // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 | ||||
| // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) | ||||
| // CHECK24-NEXT: ret void | // CHECK24-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | // CHECK24-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 | ||||
| // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) | ||||
| // CHECK24-NEXT: ret void | // CHECK24-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4 | // CHECK24-NEXT: [[TMP:%.*]] = alloca i64, align 4 | ||||
| // CHECK24-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 | // CHECK24-NEXT: [[IT:%.*]] = alloca i64, align 8 | ||||
| // CHECK24-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[LIN2:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[A3:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[A3:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK24-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 | ||||
| // CHECK24-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 4 | // CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK24-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 | // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 | ||||
| // CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[TMP1]], align 4 | // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* | ||||
| // CHECK24-NEXT: store i16 [[TMP2]], i16* [[AA]], align 2 | // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 | ||||
| // CHECK24-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 | // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 | ||||
| // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 | // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 | ||||
| // CHECK24-NEXT: store i32 [[TMP4]], i32* [[LIN]], align 4 | // CHECK24-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 | ||||
| // CHECK24-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 | |||||
| // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 | |||||
| // CHECK24-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 | |||||
| // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[LIN]], align 4 | |||||
| // CHECK24-NEXT: store i32 [[TMP7]], i32* [[DOTLINEAR_START]], align 4 | |||||
| // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 | |||||
| // CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTLINEAR_START1]], align 4 | |||||
| // CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | // CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] | ||||
| // CHECK24-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | // CHECK24-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 | ||||
| // CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | // CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 | ||||
| // CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | // CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 | ||||
| // CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | // CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 | ||||
| // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* | ||||
| // CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | // CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 | ||||
| // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) | ||||
| // CHECK24-NEXT: ret void | // CHECK24-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 | // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 | ||||
| // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[TMP:%.*]] = alloca i16, align 2 | // CHECK24-NEXT: [[TMP:%.*]] = alloca i16, align 2 | ||||
| // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 | ||||
| // CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK24-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) | ||||
| // CHECK24-NEXT: ret void | // CHECK24-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 | ||||
| // CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | // CHECK24-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 | ||||
| // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 | ||||
| ▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | // CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* | ||||
| // CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | // CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 | ||||
| // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) | ||||
| // CHECK24-NEXT: ret void | // CHECK24-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK24-NEXT: entry: | // CHECK24-NEXT: entry: | ||||
| // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | |||||
| // CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | // CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 | ||||
| // CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | // CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] | ||||
| // CHECK24: omp_if.then: | // CHECK24: omp_if.then: | ||||
| // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) | ||||
| // CHECK24-NEXT: br label [[OMP_IF_END:%.*]] | // CHECK24-NEXT: br label [[OMP_IF_END:%.*]] | ||||
| // CHECK24: omp_if.else: | // CHECK24: omp_if.else: | ||||
| // CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | // CHECK24-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) | ||||
| // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 | ||||
| // CHECK24-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.anon.4* [[OMP | |||||