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clang/test/OpenMP/nvptx_target_parallel_codegen.cpp
| Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) | // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) | ||||
| // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: worker.exit: | // CHECK1: worker.exit: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 | // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 | ||||
| Show All 36 Lines | |||||
| // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3) | // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3) | ||||
| // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: worker.exit: | // CHECK1: worker.exit: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | ||||
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| Show All 37 Lines | |||||
| // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | ||||
| // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // CHECK2: worker.exit: | // CHECK2: worker.exit: | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | ||||
| Show All 36 Lines | |||||
| // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | ||||
| // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // CHECK2: worker.exit: | // CHECK2: worker.exit: | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| Show All 37 Lines | |||||
| // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | ||||
| // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // CHECK3: worker.exit: | // CHECK3: worker.exit: | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | ||||
| Show All 36 Lines | |||||
| // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | ||||
| // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // CHECK3: worker.exit: | // CHECK3: worker.exit: | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| Show All 37 Lines | |||||
| // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) | // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) | ||||
| // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // CHECK4: worker.exit: | // CHECK4: worker.exit: | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | ||||
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 | // CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 | ||||
| // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 | // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 | ||||
| Show All 36 Lines | |||||
| // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3) | // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i64 3) | ||||
| // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // CHECK4: worker.exit: | // CHECK4: worker.exit: | ||||
| // CHECK4-NEXT: ret void | // CHECK4-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK4-NEXT: entry: | // CHECK4-NEXT: entry: | ||||
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 | ||||
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 | ||||
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| Show All 37 Lines | |||||
| // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | ||||
| // CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: worker.exit: | // CHECK5: worker.exit: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | ||||
| Show All 36 Lines | |||||
| // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | ||||
| // CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: worker.exit: | // CHECK5: worker.exit: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| Show All 37 Lines | |||||
| // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) | ||||
| // CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // CHECK6: worker.exit: | // CHECK6: worker.exit: | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | // CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 | ||||
| // CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | // CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 | ||||
| Show All 36 Lines | |||||
| // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP11]], i32 3) | ||||
| // CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // CHECK6: worker.exit: | // CHECK6: worker.exit: | ||||
| // CHECK6-NEXT: ret void | // CHECK6-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { | ||||
| // CHECK6-NEXT: entry: | // CHECK6-NEXT: entry: | ||||
| // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 | ||||
| // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 | ||||
| // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| Show All 20 Lines | |||||