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clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp
| Show All 37 Lines | |||||
| // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i64 0) | // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i64 0) | ||||
| // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: worker.exit: | // CHECK1: worker.exit: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | // CHECK1-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| Show All 18 Lines | |||||
| // CHECK1-NEXT: call void @_Z3usev() #[[ATTR6]] | // CHECK1-NEXT: call void @_Z3usev() #[[ATTR6]] | ||||
| // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: worker.exit: | // CHECK1: worker.exit: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void @_Z4workv() #[[ATTR6]] | // CHECK1-NEXT: call void @_Z4workv() #[[ATTR6]] | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | ||||
| // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | // CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | ||||
| // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 | // CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8 | ||||
| // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | ||||
| // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | // CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | ||||
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | ||||
| // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | // CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | ||||
| // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], %struct.anon.0* null) #[[ATTR3:[0-9]+]] | // CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]] | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 | // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 | ||||
| // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 | // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true) | // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true) | ||||
| // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 | // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 | ||||
| // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] | // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] | ||||
| // CHECK2: user_code.entry: | // CHECK2: user_code.entry: | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) | // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** | // CHECK2-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** | ||||
| // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i32 0) | // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i32 0) | ||||
| // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // CHECK2: worker.exit: | // CHECK2: worker.exit: | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | // CHECK2-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| Show All 18 Lines | |||||
| // CHECK2-NEXT: call void @_Z3usev() #[[ATTR6]] | // CHECK2-NEXT: call void @_Z3usev() #[[ATTR6]] | ||||
| // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // CHECK2: worker.exit: | // CHECK2: worker.exit: | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK2-NEXT: call void @_Z4workv() #[[ATTR6]] | // CHECK2-NEXT: call void @_Z4workv() #[[ATTR6]] | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | ||||
| // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | // CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | ||||
| // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 | // CHECK2-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 | ||||
| // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | ||||
| // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | // CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | ||||
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | ||||
| // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | // CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | ||||
| // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], %struct.anon.0* null) #[[ATTR3:[0-9]+]] | // CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]] | ||||
| // CHECK2-NEXT: ret void | // CHECK2-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 | // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 | ||||
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { | // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 | // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true) | // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true) | ||||
| // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 | // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 | ||||
| // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] | // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] | ||||
| // CHECK3: user_code.entry: | // CHECK3: user_code.entry: | ||||
| // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) | // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) | ||||
| // CHECK3-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** | // CHECK3-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** | ||||
| // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i32 0) | // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP2]], i32 0) | ||||
| // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 true) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // CHECK3: worker.exit: | // CHECK3: worker.exit: | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ | // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | // CHECK3-NEXT: call void @_Z3usev() #[[ATTR6:[0-9]+]] | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| Show All 18 Lines | |||||
| // CHECK3-NEXT: call void @_Z3usev() #[[ATTR6]] | // CHECK3-NEXT: call void @_Z3usev() #[[ATTR6]] | ||||
| // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 false, i1 true) | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // CHECK3: worker.exit: | // CHECK3: worker.exit: | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 | // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 | ||||
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { | // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 | ||||
| // CHECK3-NEXT: call void @_Z4workv() #[[ATTR6]] | // CHECK3-NEXT: call void @_Z4workv() #[[ATTR6]] | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper | ||||
| // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | // CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 | ||||
| // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 | // CHECK3-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4 | ||||
| // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4 | ||||
| // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | // CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2 | ||||
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4 | ||||
| // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | // CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]]) | ||||
| // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], %struct.anon.0* null) #[[ATTR3:[0-9]+]] | // CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3:[0-9]+]] | ||||
| // CHECK3-NEXT: ret void | // CHECK3-NEXT: ret void | ||||
| // | // | ||||