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Differential D106318 Diff 359913 llvm/test/CodeGen/RISCV/rv64zbp.ll

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llvm/test/CodeGen/RISCV/rv64zbp.ll

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; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: addiw a1, a1, -241 ; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a1, a1, 4 ; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: lui a2, 241 ; RV64I-NEXT: lui a2, 1044721
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 36
; RV64I-NEXT: addi a2, a2, 240 ; RV64I-NEXT: srli a2, a2, 32
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 209715 ; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819 ; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: lui a2, 838861 ; RV64I-NEXT: lui a2, 838861
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; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a2, a2, 4 ; RV64I-NEXT: slli a2, a2, 4
; RV64I-NEXT: lui a3, 241 ; RV64I-NEXT: lui a3, 1044721
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 36
; RV64I-NEXT: addi a3, a3, 240 ; RV64I-NEXT: srli a3, a3, 32
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819 ; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a2, a2, 2 ; RV64I-NEXT: slli a2, a2, 2
; RV64I-NEXT: lui a3, 838861 ; RV64I-NEXT: lui a3, 838861
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; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: addiw a1, a1, -241 ; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a1, a1, 4 ; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: lui a3, 241 ; RV64I-NEXT: lui a3, 1044721
; RV64I-NEXT: addiw a3, a3, -241 ; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: slli a3, a3, 12 ; RV64I-NEXT: slli a3, a3, 36
; RV64I-NEXT: addi a3, a3, 240 ; RV64I-NEXT: srli a3, a3, 32
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srli a0, a0, 4 ; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 209715 ; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819 ; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: lui a3, 838861 ; RV64I-NEXT: lui a3, 838861
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; RV64I-NEXT: lui a1, 983041 ; RV64I-NEXT: lui a1, 983041
; RV64I-NEXT: slli a1, a1, 4 ; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: addi a1, a1, -1 ; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: slli a1, a1, 24 ; RV64I-NEXT: slli a1, a1, 24
; RV64I-NEXT: addi a1, a1, 255 ; RV64I-NEXT: addi a1, a1, 255
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: addi a3, zero, 255 ; RV64I-NEXT: addi a3, zero, 255
; RV64I-NEXT: slli a4, a3, 32 ; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addi a4, a4, 255 ; RV64I-NEXT: addi a3, a3, 255
; RV64I-NEXT: slli a4, a4, 16 ; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: addi a3, zero, -1
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addi a3, a3, 255
; RV64I-NEXT: slli a3, a3, 24 ; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: addi a3, a3, 1 ; RV64I-NEXT: srli a3, a3, 16
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: shfl8_i64: ; RV64IB-LABEL: shfl8_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: zip8.w a0, a0 ; RV64IB-NEXT: zip8.w a0, a0
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