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	; RV64IBA-NEXT: zext.w a0, a0			; RV64IBA-NEXT: zext.w a0, a0
	; RV64IBA-NEXT: ret			; RV64IBA-NEXT: ret
	ret i64 4294967294 ; -2 in 32 bits.			ret i64 4294967294 ; -2 in 32 bits.
	}			}

	define i64 @imm_zextw2() nounwind {			define i64 @imm_zextw2() nounwind {
	; RV64I-LABEL: imm_zextw2:			; RV64I-LABEL: imm_zextw2:
	; RV64I: # %bb.0:			; RV64I: # %bb.0:
	; RV64I-NEXT: lui a0, 171			; RV64I-NEXT: lui a0, 873813
	; RV64I-NEXT: addiw a0, a0, -1365			; RV64I-NEXT: addiw a0, a0, 1365
	; RV64I-NEXT: slli a0, a0, 12			; RV64I-NEXT: slli a0, a0, 33
	; RV64I-NEXT: addi a0, a0, -1366			; RV64I-NEXT: srli a0, a0, 32
	; RV64I-NEXT: ret			; RV64I-NEXT: ret
	;			;
	; RV64IB-LABEL: imm_zextw2:			; RV64IB-LABEL: imm_zextw2:
	; RV64IB: # %bb.0:			; RV64IB: # %bb.0:
	; RV64IB-NEXT: lui a0, 699051			; RV64IB-NEXT: lui a0, 699051
	; RV64IB-NEXT: addiw a0, a0, -1366			; RV64IB-NEXT: addiw a0, a0, -1366
	; RV64IB-NEXT: zext.w a0, a0			; RV64IB-NEXT: zext.w a0, a0
	; RV64IB-NEXT: ret			; RV64IB-NEXT: ret
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