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llvm/test/CodeGen/RISCV/div.ll
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload | ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload | ||||
; RV64I-NEXT: addi sp, sp, 16 | ; RV64I-NEXT: addi sp, sp, 16 | ||||
; RV64I-NEXT: ret | ; RV64I-NEXT: ret | ||||
; | ; | ||||
; RV64IM-LABEL: udiv_constant: | ; RV64IM-LABEL: udiv_constant: | ||||
; RV64IM: # %bb.0: | ; RV64IM: # %bb.0: | ||||
; RV64IM-NEXT: slli a0, a0, 32 | ; RV64IM-NEXT: slli a0, a0, 32 | ||||
; RV64IM-NEXT: srli a0, a0, 32 | ; RV64IM-NEXT: srli a0, a0, 32 | ||||
; RV64IM-NEXT: lui a1, 205 | ; RV64IM-NEXT: lui a1, 838861 | ||||
; RV64IM-NEXT: addiw a1, a1, -819 | ; RV64IM-NEXT: addiw a1, a1, -819 | ||||
; RV64IM-NEXT: slli a1, a1, 12 | ; RV64IM-NEXT: slli a1, a1, 32 | ||||
; RV64IM-NEXT: addi a1, a1, -819 | ; RV64IM-NEXT: srli a1, a1, 32 | ||||
; RV64IM-NEXT: mul a0, a0, a1 | ; RV64IM-NEXT: mul a0, a0, a1 | ||||
; RV64IM-NEXT: srli a0, a0, 34 | ; RV64IM-NEXT: srli a0, a0, 34 | ||||
; RV64IM-NEXT: ret | ; RV64IM-NEXT: ret | ||||
%1 = udiv i32 %a, 5 | %1 = udiv i32 %a, 5 | ||||
ret i32 %1 | ret i32 %1 | ||||
} | } | ||||
define i32 @udiv_pow2(i32 %a) nounwind { | define i32 @udiv_pow2(i32 %a) nounwind { | ||||
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