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llvm/lib/Target/PowerPC/PPCInstr64Bit.td
| Show First 20 Lines • Show All 298 Lines • ▼ Show 20 Lines | def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), | ||||
| "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; | "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; | ||||
| // TODO: Add scheduling info. | // TODO: Add scheduling info. | ||||
| let hasNoSchedulingInfo = 1 in | let hasNoSchedulingInfo = 1 in | ||||
| def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), | def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), | ||||
| "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, | "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, | ||||
| isPPC64, isRecordForm; | isPPC64, isRecordForm; | ||||
| } | } | ||||
| def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), | |||||
| (ins g8prc:$src), | |||||
| "#SPLIT_QUADWORD", []>; | |||||
| class AtomicRMW128<string asmstr> | |||||
| : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), | |||||
| (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), | |||||
| asmstr, []>; | |||||
| // We have to keep values in MI's uses during LL/SC looping as they are, | |||||
| // so set both $RTp and $scratch earlyclobber. | |||||
| let mayStore = 1, mayLoad = 1, | |||||
| Defs = [CR0], | |||||
| Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { | |||||
efriedma: Do you need to specify the size of these instructions somewhere, if you're expanding them after… | |||||
Good point. There is PPCBranchSelector pass serves as branch relaxation and PowerPC hasn't implemented LLVM MC's branch relaxation. I should have put the expansion before PPCBranchSelector. lkail: Good point. There is `PPCBranchSelector` pass serves as branch relaxation and PowerPC hasn't… | |||||
| // Atomic pseudo instructions expanded post-ra. | |||||
| def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; | |||||
| def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; | |||||
| def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; | |||||
| def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; | |||||
| def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; | |||||
| def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; | |||||
| def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; | |||||
| def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< | |||||
| (outs g8prc:$RTp, g8prc:$scratch), | |||||
| (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, | |||||
| g8rc:$new_lo, g8rc:$new_hi), | |||||
| "#ATOMIC_CMP_SWAP_I128", []>; | |||||
| } | |||||
| def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, | |||||
| i64:$incr_lo, | |||||
| i64:$incr_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, | |||||
| g8rc:$incr_lo, | |||||
| g8rc:$incr_hi))>; | |||||
| def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, | |||||
| i64:$cmp_lo, | |||||
| i64:$cmp_hi, | |||||
| i64:$new_lo, | |||||
| i64:$new_hi), | |||||
| (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 | |||||
| memrr:$ptr, | |||||
| g8rc:$cmp_lo, | |||||
| g8rc:$cmp_hi, | |||||
| g8rc:$new_lo, | |||||
| g8rc:$new_hi))>; | |||||
| let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in | let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in | ||||
| def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), | def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), | ||||
| "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, | "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, | ||||
| Requires<[IsISA3_0]>; | Requires<[IsISA3_0]>; | ||||
| let Interpretation64Bit = 1, isCodeGenOnly = 1 in { | let Interpretation64Bit = 1, isCodeGenOnly = 1 in { | ||||
| let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in | ||||
| def TCRETURNdi8 :PPCEmitTimePseudo< (outs), | def TCRETURNdi8 :PPCEmitTimePseudo< (outs), | ||||
| ▲ Show 20 Lines • Show All 1,413 Lines • Show Last 20 Lines | |||||
Do you need to specify the size of these instructions somewhere, if you're expanding them after branch relaxation?