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llvm/tools/opt/opt.cpp
| Show First 20 Lines • Show All 507 Lines • ▼ Show 20 Lines | std::vector<StringRef> PassNamePrefix = { | ||||
| "x86-", "xcore-", "wasm-", "systemz-", "ppc-", "nvvm-", "nvptx-", | "x86-", "xcore-", "wasm-", "systemz-", "ppc-", "nvvm-", "nvptx-", | ||||
| "mips-", "lanai-", "hexagon-", "bpf-", "avr-", "thumb2-", "arm-", | "mips-", "lanai-", "hexagon-", "bpf-", "avr-", "thumb2-", "arm-", | ||||
| "si-", "gcn-", "amdgpu-", "aarch64-", "amdgcn-", "polly-"}; | "si-", "gcn-", "amdgpu-", "aarch64-", "amdgcn-", "polly-"}; | ||||
| std::vector<StringRef> PassNameContain = {"ehprepare"}; | std::vector<StringRef> PassNameContain = {"ehprepare"}; | ||||
| std::vector<StringRef> PassNameExact = { | std::vector<StringRef> PassNameExact = { | ||||
| "safe-stack", "cost-model", | "safe-stack", "cost-model", | ||||
| "codegenprepare", "interleaved-load-combine", | "codegenprepare", "interleaved-load-combine", | ||||
| "unreachableblockelim", "verify-safepoint-ir", | "unreachableblockelim", "verify-safepoint-ir", | ||||
| "atomic-expand", | "atomic-expand", "expandvp", | ||||
| "hardware-loops", "type-promotion", | "hardware-loops", "type-promotion", | ||||
| "mve-tail-predication", "interleaved-access", | "mve-tail-predication", "interleaved-access", | ||||
| "global-merge", "pre-isel-intrinsic-lowering", | "global-merge", "pre-isel-intrinsic-lowering", | ||||
| "expand-reductions", "indirectbr-expand", | "expand-reductions", "indirectbr-expand", | ||||
| "generic-to-nvvm", "expandmemcmp", | "generic-to-nvvm", "expandmemcmp", | ||||
| "loop-reduce", "lower-amx-type", | "loop-reduce", "lower-amx-type", | ||||
| "lower-amx-intrinsics", "polyhedral-info", | "lower-amx-intrinsics", "polyhedral-info", | ||||
| "replace-with-veclib"}; | "replace-with-veclib"}; | ||||
| ▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | int main(int argc, char **argv) { | ||||
| initializeGlobalMergePass(Registry); | initializeGlobalMergePass(Registry); | ||||
| initializeIndirectBrExpandPassPass(Registry); | initializeIndirectBrExpandPassPass(Registry); | ||||
| initializeInterleavedLoadCombinePass(Registry); | initializeInterleavedLoadCombinePass(Registry); | ||||
| initializeInterleavedAccessPass(Registry); | initializeInterleavedAccessPass(Registry); | ||||
| initializeEntryExitInstrumenterPass(Registry); | initializeEntryExitInstrumenterPass(Registry); | ||||
| initializePostInlineEntryExitInstrumenterPass(Registry); | initializePostInlineEntryExitInstrumenterPass(Registry); | ||||
| initializeUnreachableBlockElimLegacyPassPass(Registry); | initializeUnreachableBlockElimLegacyPassPass(Registry); | ||||
| initializeExpandReductionsPass(Registry); | initializeExpandReductionsPass(Registry); | ||||
| initializeExpandVectorPredicationPass(Registry); | |||||
| initializeWasmEHPreparePass(Registry); | initializeWasmEHPreparePass(Registry); | ||||
| initializeWriteBitcodePassPass(Registry); | initializeWriteBitcodePassPass(Registry); | ||||
| initializeHardwareLoopsPass(Registry); | initializeHardwareLoopsPass(Registry); | ||||
| initializeTypePromotionPass(Registry); | initializeTypePromotionPass(Registry); | ||||
| initializeReplaceWithVeclibLegacyPass(Registry); | initializeReplaceWithVeclibLegacyPass(Registry); | ||||
| #ifdef BUILD_EXAMPLES | #ifdef BUILD_EXAMPLES | ||||
| initializeExampleIRTransforms(Registry); | initializeExampleIRTransforms(Registry); | ||||
| ▲ Show 20 Lines • Show All 513 Lines • Show Last 20 Lines | |||||