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Differential D99083 Diff 339103 llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 532 Lines • ▼ Show 20 Lines foreach nf = NFList<m>.L in {
def "VRN" # nf # "M" # m: VReg<[untyped], def "VRN" # nf # "M" # m: VReg<[untyped],
(add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), (add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
!mul(nf, m)>; !mul(nf, m)>;
def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
(add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
!mul(nf, m)>; !mul(nf, m)>;
} }
} }
// Special registers
def FFLAGS : RISCVReg<0, "fflags">;
craig.topperUnsubmitted
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Is there any significance the 1, 2, and 3 chosen for the first operand here?

craig.topper: Is there any significance the 1, 2, and 3 chosen for the first operand here?
sepavloffAuthorUnsubmitted
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The first operand of RISCVReg is HWEncoding, 1, 2 and 3 represent hardware addresses of the respective system registers which are specified in the RISCV specification (https://github.com/riscv/riscv-isa-manual/releases/download/draft-20210402-1271737/riscv-spec.pdf), chapter 25 (RV32/64G Instruction Set Listings), table 25.3 (RISC-V control and status register (CSR) address map).

On the other hand, these special registers are not used as operands in any of non-pseudo instruction, so these definitions are not used in instruction emitter. It means that particular values are not important, at least now.

sepavloff: The first operand of `RISCVReg` is `HWEncoding`, 1, 2 and 3 represent hardware addresses of the…
craig.topperUnsubmitted
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I think these should probably just be 0 like the flags registers on other targets. It's only a 5 bit field and the CSR addresses are 12 bits so its purely a coincidence that these CSRs happen to be representable in 5 bits.

craig.topper: I think these should probably just be 0 like the flags registers on other targets. It's only a…
def FRM : RISCVReg<0, "frm">;
def FCSR : RISCVReg<0, "fcsr">;