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Differential D97637 Diff 326995 llvm/test/CodeGen/X86/shift-double.ll

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llvm/test/CodeGen/X86/shift-double.ll

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%and = zext i8 %tand to i32 %and = zext i8 %tand to i32
%and64 = zext i8 %tand64 to i32 %and64 = zext i8 %tand64 to i32
%sh_lo = lshr i32 %lo, %and64 %sh_lo = lshr i32 %lo, %and64
%sh_hi = shl i32 %hi, %and %sh_hi = shl i32 %hi, %and
%sh = or i32 %sh_lo, %sh_hi %sh = or i32 %sh_lo, %sh_hi
ret i32 %sh ret i32 %sh
} }
; PR34641 - Masked Shift Counts ; These are not valid shld/shrd patterns. When the shift amount modulo
; the bitwidth is zero, the result should be an OR of both operands not a
; shift.
define i32 @shld_safe_i32(i32, i32, i32) { define i32 @not_shld_i32(i32, i32, i32) {
lebedev.riUnsubmitted
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Indeed:
https://godbolt.org/z/641T9c
https://alive2.llvm.org/ce/z/5eK7nf

lebedev.ri: Indeed: https://godbolt.org/z/641T9c https://alive2.llvm.org/ce/z/5eK7nf
RKSimonUnsubmitted
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probably not "safe" then......

RKSimon: probably not "safe" then......
; X86-LABEL: shld_safe_i32: ; X86-LABEL: not_shld_i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll %cl, %edx
; X86-NEXT: shldl %cl, %edx, %eax ; X86-NEXT: negb %cl
; X86-NEXT: shrl %cl, %eax
; X86-NEXT: orl %edx, %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: shld_safe_i32: ; X64-LABEL: not_shld_i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %edx, %ecx
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %esi, %eax
; X64-NEXT: shll %cl, %edi
; X64-NEXT: negb %cl
; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shldl %cl, %esi, %eax ; X64-NEXT: shrl %cl, %eax
; X64-NEXT: orl %edi, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%4 = and i32 %2, 31 %4 = and i32 %2, 31
%5 = shl i32 %0, %4 %5 = shl i32 %0, %4
%6 = sub i32 0, %2 %6 = sub i32 0, %2
%7 = and i32 %6, 31 %7 = and i32 %6, 31
%8 = lshr i32 %1, %7 %8 = lshr i32 %1, %7
%9 = or i32 %5, %8 %9 = or i32 %5, %8
ret i32 %9 ret i32 %9
} }
define i32 @shrd_safe_i32(i32, i32, i32) { define i32 @not_shrd_i32(i32, i32, i32) {
; X86-LABEL: shrd_safe_i32: ; X86-LABEL: not_shrd_i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shrl %cl, %edx
; X86-NEXT: shrdl %cl, %edx, %eax ; X86-NEXT: negb %cl
; X86-NEXT: shll %cl, %eax
; X86-NEXT: orl %edx, %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: shrd_safe_i32: ; X64-LABEL: not_shrd_i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %edx, %ecx
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %esi, %eax
; X64-NEXT: shrl %cl, %edi
; X64-NEXT: negb %cl
; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NEXT: shrdl %cl, %esi, %eax ; X64-NEXT: shll %cl, %eax
; X64-NEXT: orl %edi, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%4 = and i32 %2, 31 %4 = and i32 %2, 31
%5 = lshr i32 %0, %4 %5 = lshr i32 %0, %4
%6 = sub i32 0, %2 %6 = sub i32 0, %2
%7 = and i32 %6, 31 %7 = and i32 %6, 31
%8 = shl i32 %1, %7 %8 = shl i32 %1, %7
%9 = or i32 %5, %8 %9 = or i32 %5, %8
ret i32 %9 ret i32 %9
} }