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Differential D96340 Diff 323224 llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll

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llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll

; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx803 -O0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx803 -O0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
define void @child_function() #0 { define void @child_function() #0 {
call void asm sideeffect "", "~{vcc}" () #0 call void asm sideeffect "", "~{vcc}" () #0
ret void ret void
} }
; GCN-LABEL: {{^}}reserve_vgpr_with_no_lower_vgpr_available: ; GCN-LABEL: {{^}}reserve_vgpr_with_no_lower_vgpr_available:
; GCN: buffer_store_dword v255, off, s[0:3], s32 ; GCN: buffer_store_dword v255, off, s[0:3], s32
; GCN: v_writelane_b32 v255, s33, 2 ; GCN: v_writelane_b32 v255, s33, 2
; GCN: v_writelane_b32 v255, s30, 0 ; GCN: v_writelane_b32 v255, s30, 0
; GCN: v_writelane_b32 v255, s31, 1 ; GCN: v_writelane_b32 v255, s31, 1
; GCN: s_swappc_b64 s[30:31], s[4:5] ; GCN: s_swappc_b64 s[30:31], s[16:17]
; GCN: v_readlane_b32 s30, v255, 0 ; GCN: v_readlane_b32 s30, v255, 0
; GCN: v_readlane_b32 s31, v255, 1 ; GCN: v_readlane_b32 s31, v255, 1
; GCN: v_readlane_b32 s33, v255, 2 ; GCN: v_readlane_b32 s33, v255, 2
; GCN: ; NumVgprs: 256 ; GCN: ; NumVgprs: 256
define void @reserve_vgpr_with_no_lower_vgpr_available() #0 { define void @reserve_vgpr_with_no_lower_vgpr_available() #0 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
Show All 29 Linesdefine void @reserve_vgpr_with_no_lower_vgpr_available() #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}reserve_lowest_available_vgpr: ; GCN-LABEL: {{^}}reserve_lowest_available_vgpr:
; GCN: buffer_store_dword v254, off, s[0:3], s32 ; GCN: buffer_store_dword v254, off, s[0:3], s32
; GCN: v_writelane_b32 v254, s33, 2 ; GCN: v_writelane_b32 v254, s33, 2
; GCN: v_writelane_b32 v254, s30, 0 ; GCN: v_writelane_b32 v254, s30, 0
; GCN: v_writelane_b32 v254, s31, 1 ; GCN: v_writelane_b32 v254, s31, 1
; GCN: s_swappc_b64 s[30:31], s[4:5] ; GCN: s_swappc_b64 s[30:31], s[16:17]
; GCN: v_readlane_b32 s30, v254, 0 ; GCN: v_readlane_b32 s30, v254, 0
; GCN: v_readlane_b32 s31, v254, 1 ; GCN: v_readlane_b32 s31, v254, 1
; GCN: v_readlane_b32 s33, v254, 2 ; GCN: v_readlane_b32 s33, v254, 2
define void @reserve_lowest_available_vgpr() #0 { define void @reserve_lowest_available_vgpr() #0 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
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ret: ret:
ret void ret void
} }
; GCN-LABEL: {{^}}reserve_vgpr_with_tail_call ; GCN-LABEL: {{^}}reserve_vgpr_with_tail_call
; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32 ; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32
; GCN-NOT: v_writelane ; GCN-NOT: v_writelane
; GCN: s_setpc_b64 s[4:5] ; GCN: s_setpc_b64 s[16:17]
define void @reserve_vgpr_with_tail_call() #0 { define void @reserve_vgpr_with_tail_call() #0 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
call void asm sideeffect "", call void asm sideeffect "",
"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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