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Differential D96340 Diff 323224 llvm/test/CodeGen/AMDGPU/ipra.ll

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llvm/test/CodeGen/AMDGPU/ipra.ll

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; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NOT: buffer_store ; GCN-NOT: buffer_store
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-NOT: readlane ; GCN-NOT: readlane
; GCN-NOT: writelane ; GCN-NOT: writelane
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
; GCN: ; NumSgprs: 37 ; GCN: ; NumSgprs: 37
; GCN: ; NumVgprs: 9 ; GCN: ; NumVgprs: 32
define amdgpu_kernel void @kernel_call() #0 { define amdgpu_kernel void @kernel_call() #0 {
%vgpr = load volatile i32, i32 addrspace(1)* undef %vgpr = load volatile i32, i32 addrspace(1)* undef
tail call void @func() tail call void @func()
store volatile i32 %vgpr, i32 addrspace(1)* undef store volatile i32 %vgpr, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_regular_call: ; GCN-LABEL: {{^}}func_regular_call:
; GCN-NOT: buffer_store ; GCN-NOT: buffer_store
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-NOT: readlane ; GCN-NOT: readlane
; GCN-NOT: writelane ; GCN-NOT: writelane
; GCN: flat_load_dword v8 ; GCN: flat_load_dword v8
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NOT: buffer_store ; GCN-NOT: buffer_store
; GCN-NOT: buffer_load ; GCN-NOT: buffer_load
; GCN-NOT: readlane ; GCN-NOT: readlane
; GCN-NOT: writelane ; GCN-NOT: writelane
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
; GCN: ; NumSgprs: 32 ; GCN: ; NumSgprs: 32
; GCN: ; NumVgprs: 9 ; GCN: ; NumVgprs: 32
define void @func_regular_call() #1 { define void @func_regular_call() #1 {
%vgpr = load volatile i32, i32 addrspace(1)* undef %vgpr = load volatile i32, i32 addrspace(1)* undef
tail call void @func() tail call void @func()
store volatile i32 %vgpr, i32 addrspace(1)* undef store volatile i32 %vgpr, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_tail_call: ; GCN-LABEL: {{^}}func_tail_call:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s4, ; GCN-NEXT: s_add_u32 s16,
; GCN-NEXT: s_addc_u32 s5, ; GCN-NEXT: s_addc_u32 s17,
; GCN-NEXT: s_setpc_b64 s[4:5] ; GCN-NEXT: s_setpc_b64 s[16:17]
; GCN: ; NumSgprs: 32 ; GCN: ; NumSgprs: 32
; GCN: ; NumVgprs: 8 ; GCN: ; NumVgprs: 32
define void @func_tail_call() #1 { define void @func_tail_call() #1 {
tail call void @func() tail call void @func()
ret void ret void
} }
; GCN-LABEL: {{^}}func_call_tail_call: ; GCN-LABEL: {{^}}func_call_tail_call:
; GCN: flat_load_dword v8 ; GCN: flat_load_dword v8
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
; GCN: ; NumSgprs: 32 ; GCN: ; NumSgprs: 32
; GCN: ; NumVgprs: 9 ; GCN: ; NumVgprs: 32
define void @func_call_tail_call() #1 { define void @func_call_tail_call() #1 {
%vgpr = load volatile i32, i32 addrspace(1)* undef %vgpr = load volatile i32, i32 addrspace(1)* undef
tail call void @func() tail call void @func()
store volatile i32 %vgpr, i32 addrspace(1)* undef store volatile i32 %vgpr, i32 addrspace(1)* undef
tail call void @func() tail call void @func()
ret void ret void
} }
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