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Differential D96340 Diff 323224 llvm/test/CodeGen/AMDGPU/call-argument-types.ll

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llvm/test/CodeGen/AMDGPU/call-argument-types.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
call void @external_void_func_i1(i1 true) call void @external_void_func_i1(i1 true)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i1_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_signext:
; HSA: buffer_load_ubyte [[VAR:v[0-9]+]] ; HSA: buffer_load_ubyte [[VAR:v[0-9]+]]
; HSA: s_mov_b32 s32, 0 ; HSA-DAG: s_mov_b32 s32, 0
; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]] ; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]]
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1 ; MESA-DAG: v_bfe_i32 v0, v0, 0, 1
; HSA: v_bfe_i32 v0, v3, 0, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_signext(i1 %var) call void @external_void_func_i1_signext(i1 %var)
ret void ret void
} }
; FIXME: load should be scheduled before getpc ; FIXME: load should be scheduled before getpc
; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext:
; HSA: buffer_load_ubyte v0 ; HSA: buffer_load_ubyte v3
; HSA-DAG: s_mov_b32 s32, 0{{$}} ; HSA-DAG: s_mov_b32 s32, 0{{$}}
; MESA: buffer_load_ubyte v0 ; MESA: buffer_load_ubyte v0
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; MESA: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4 ; MESA-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12 ; MESA-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12
; GCN-NEXT: v_and_b32_e32 v0, 1, v0 ; MESA-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; MESA-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; MESA-NEXT: s_endpgm
; HSA: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; HSA-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
; HSA-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12
; HSA-NEXT: v_and_b32_e32 v0, 1, v3
; HSA-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; HSA-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_zeroext(i1 %var) call void @external_void_func_i1_zeroext(i1 %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm:
Show All 9 Lines
define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
call void @external_void_func_i8(i8 123) call void @external_void_func_i8(i8 123)
ret void ret void
} }
; FIXME: don't wait before call ; FIXME: don't wait before call
; GCN-LABEL: {{^}}test_call_external_void_func_i8_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_signext:
; GCN-DAG: buffer_load_sbyte v0 ; MESA-DAG: buffer_load_sbyte v0
; HSA-DAG: buffer_load_sbyte v3
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-DAG: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
%var = load volatile i8, i8 addrspace(1)* undef %var = load volatile i8, i8 addrspace(1)* undef
call void @external_void_func_i8_signext(i8 %var) call void @external_void_func_i8_signext(i8 %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i8_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i8_zeroext:
; GCN-DAG: buffer_load_ubyte v0 ; MESA-DAG: buffer_load_ubyte v0
; HSA-DAG: buffer_load_ubyte v3
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-DAG: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
%var = load volatile i8, i8 addrspace(1)* undef %var = load volatile i8, i8 addrspace(1)* undef
call void @external_void_func_i8_zeroext(i8 %var) call void @external_void_func_i8_zeroext(i8 %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_imm:
; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}} ; GCN-DAG: v_mov_b32_e32 v0, 0x7b{{$}}
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
call void @external_void_func_i16(i16 123) call void @external_void_func_i16(i16 123)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_signext: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_signext:
; GCN-DAG: buffer_load_sshort v0 ; MESA-DAG: buffer_load_sshort v0
; HSA-DAG: buffer_load_sshort v3
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-DAG: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
%var = load volatile i16, i16 addrspace(1)* undef %var = load volatile i16, i16 addrspace(1)* undef
call void @external_void_func_i16_signext(i16 %var) call void @external_void_func_i16_signext(i16 %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i16_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i16_zeroext:
; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4 ; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4
; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+12 ; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+12
; GCN-DAG: s_mov_b32 s32, 0 ; GCN-DAG: s_mov_b32 s32, 0
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-DAG: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
%var = load volatile i16, i16 addrspace(1)* undef %var = load volatile i16, i16 addrspace(1)* undef
call void @external_void_func_i16_zeroext(i16 %var) call void @external_void_func_i16_zeroext(i16 %var)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm:
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 { define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
call void @external_void_func_v2i32(<2 x i32> <i32 1, i32 2>) call void @external_void_func_v2i32(<2 x i32> <i32 1, i32 2>)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v3i32_imm: {{.*}} ; GCN-LABEL: {{^}}test_call_external_void_func_v3i32_imm: {{.*}}
; GCN-NOT: v3 ; GCN-NOT: v3,
; GCN-DAG: v_mov_b32_e32 v0, 3 ; GCN-DAG: v_mov_b32_e32 v0, 3
; GCN-DAG: v_mov_b32_e32 v1, 4 ; GCN-DAG: v_mov_b32_e32 v1, 4
; GCN-DAG: v_mov_b32_e32 v2, 5 ; GCN-DAG: v_mov_b32_e32 v2, 5
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
call void @external_void_func_v3i32(<3 x i32> <i32 3, i32 4, i32 5>) call void @external_void_func_v3i32(<3 x i32> <i32 3, i32 4, i32 5>)
ret void ret void
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; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN-DAG: buffer_load_dwordx4 v[16:19], off ; GCN-DAG: buffer_load_dwordx4 v[16:19], off
; GCN-DAG: buffer_load_dwordx4 v[20:23], off ; GCN-DAG: buffer_load_dwordx4 v[20:23], off
; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN-NOT: s_waitcnt ; MESA-NOT: s_waitcnt
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 { define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
%ptr = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef %ptr = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
%val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr %val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr
call void @external_void_func_v32i32(<32 x i32> %val) call void @external_void_func_v32i32(<32 x i32> %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v32i32_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_v32i32_i32:
; HSA-NOT: s_add_u32 s32 ; HSA-NOT: s_add_u32 s32
; MESA-NOT: s_add_u32 s32 ; MESA-NOT: s_add_u32 s32
; GCN-DAG: buffer_load_dword [[VAL1:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} ; GCN-DAG: buffer_load_dword [[VAL1:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN-DAG: buffer_load_dwordx4 v[16:19], off ; GCN-DAG: buffer_load_dwordx4 v[16:19], off
; GCN-DAG: buffer_load_dwordx4 v[20:23], off ; GCN-DAG: buffer_load_dwordx4 v[20:23], off
; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: buffer_store_dword [[VAL1]], off, s[{{[0-9]+}}:{{[0-9]+}}], s32{{$}} ; MESA: buffer_store_dword [[VAL1]], off, s[{{[0-9]+}}:{{[0-9]+}}], s32{{$}}
; HSA: buffer_store_dword [[VAL1]], off, s[{{[0-9]+}}:{{[0-9]+}}], s32 offset:4
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
%ptr0 = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef %ptr0 = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
%val0 = load <32 x i32>, <32 x i32> addrspace(1)* %ptr0 %val0 = load <32 x i32>, <32 x i32> addrspace(1)* %ptr0
%val1 = load i32, i32 addrspace(1)* undef %val1 = load i32, i32 addrspace(1)* undef
call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1) call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_i32_func_i32_imm: ; GCN-LABEL: {{^}}test_call_external_i32_func_i32_imm:
; GCN: v_mov_b32_e32 v0, 42 ; GCN: v_mov_b32_e32 v0, 42
; GCN: s_swappc_b64 s[30:31], ; GCN: s_swappc_b64 s[30:31],
; GCN-NOT: s_waitcnt ; GCN-NOT: s_waitcnt
; GCN: buffer_store_dword v0, off, s[36:39], 0 ; GCN: buffer_store_dword v0, off, s[36:39], 0
define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {
%val = call i32 @external_i32_func_i32(i32 42) %val = call i32 @external_i32_func_i32(i32 42)
store volatile i32 %val, i32 addrspace(1)* %out store volatile i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_struct_i8_i32:
; GCN: buffer_load_ubyte v0, off ; MESA: buffer_load_ubyte v0, off
; GCN: buffer_load_dword v1, off ; MESA-DAG: buffer_load_dword v1, off
; GCN-NOT: s_waitcnt ; HSA: buffer_load_ubyte v3, off
; HSA-DAG: buffer_load_dword v4, off
; MESA-NOT: s_waitcnt
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 { define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
%ptr0 = load { i8, i32 } addrspace(1)*, { i8, i32 } addrspace(1)* addrspace(4)* undef %ptr0 = load { i8, i32 } addrspace(1)*, { i8, i32 } addrspace(1)* addrspace(4)* undef
%val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0 %val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0
call void @external_void_func_struct_i8_i32({ i8, i32 } %val) call void @external_void_func_struct_i8_i32({ i8, i32 } %val)
ret void ret void
} }
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; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 { define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
entry: entry:
call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp) call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}tail_call_byval_align16: ; GCN-LABEL: {{^}}tail_call_byval_align16:
; GCN-NOT: s32 ; GCN-NOT: s32,
; GCN: buffer_load_dword [[VREG1:v[0-9]+]], off, s[0:3], s32 offset:8 ; MESA: buffer_load_dword [[VREG1:v[0-9]+]], off, s[0:3], s32 offset:8
; GCN: buffer_load_dword [[VREG2:v[0-9]+]], off, s[0:3], s32 offset:12 ; MESA: buffer_load_dword [[VREG2:v[0-9]+]], off, s[0:3], s32 offset:12
; HSA: buffer_load_dword [[VREG1:v[0-9]+]], off, s[0:3], s32
; HSA: buffer_load_dword [[VREG2:v[0-9]+]], off, s[0:3], s32 offset:24
; GCN: s_getpc_b64 ; GCN: s_getpc_b64
; GCN: buffer_store_dword [[VREG2]], off, s[0:3], s32 offset:4 ; MESA: buffer_store_dword [[VREG2]], off, s[0:3], s32 offset:4
; GCN: buffer_store_dword [[VREG1]], off, s[0:3], s32{{$}} ; MESA: buffer_store_dword [[VREG1]], off, s[0:3], s32{{$}}
; GCN-NOT: s32 ; HSA: buffer_store_dword [[VREG2]], off, s[0:3], s32 offset:16
; HSA: buffer_store_dword [[VREG1]], off, s[0:3], s32
; GCN-NOT: s32,
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
entry: entry:
%alloca = alloca double, align 8, addrspace(5) %alloca = alloca double, align 8, addrspace(5)
tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca) tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca)
ret void ret void
} }
; GCN-LABEL: {{^}}tail_call_stack_passed_arg_alignment_v32i32_f64: ; GCN-LABEL: {{^}}tail_call_stack_passed_arg_alignment_v32i32_f64:
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; MESA: buffer_load_dword v32, off, s[0:3], s32 offset:4
; GCN: buffer_load_dword v33, off, s[0:3], s32{{$}} ; MESA: buffer_load_dword v33, off, s[0:3], s32{{$}}
; GCN: s_getpc_b64 ; MESA: s_getpc_b64
; GCN: buffer_store_dword v33, off, s[0:3], s32{{$}} ; MESA: buffer_store_dword v33, off, s[0:3], s32{{$}}
; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:4 ; MESA: buffer_store_dword v32, off, s[0:3], s32 offset:4
; HSA: buffer_load_dword v32, off, s[0:3], s32 offset:8
; HSA: buffer_load_dword v33, off, s[0:3], s32 offset:4
; HSA: s_getpc_b64
; HSA: buffer_store_dword v33, off, s[0:3], s32 offset:4
; HSA: buffer_store_dword v32, off, s[0:3], s32 offset:8
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @tail_call_stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 { define void @tail_call_stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
entry: entry:
tail call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp) tail call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}stack_12xv3i32: ; GCN-LABEL: {{^}}stack_12xv3i32:
; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 12 ; MESA: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
; GCN: buffer_store_dword [[REG12]], {{.*$}} ; MESA: buffer_store_dword [[REG12]], {{.*$}}
; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 13 ; MESA: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
; GCN: buffer_store_dword [[REG13]], {{.*}} offset:4 ; MESA: buffer_store_dword [[REG13]], {{.*}} offset:4
; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 14 ; MESA: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
; GCN: buffer_store_dword [[REG14]], {{.*}} offset:8 ; MESA: buffer_store_dword [[REG14]], {{.*}} offset:8
; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 15 ; MESA: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
; GCN: buffer_store_dword [[REG15]], {{.*}} offset:12 ; MESA: buffer_store_dword [[REG15]], {{.*}} offset:12
; GCN: v_mov_b32_e32 v31, 11 ; MESA: v_mov_b32_e32 v31, 11
; GCN: s_getpc ; MESA: s_getpc
; HSA: v_mov_b32_e32 [[REG12:v[0-9]+]], 11
; HSA: buffer_store_dword [[REG12]], {{.*$}}
; HSA: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
; HSA: buffer_store_dword [[REG12]], {{.*}} offset:4
; HSA: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
; HSA: buffer_store_dword [[REG13]], {{.*}} offset:8
; HSA: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
; HSA: buffer_store_dword [[REG14]], {{.*}} offset:12
; HSA: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
; HSA: buffer_store_dword [[REG15]], {{.*}} offset:16
; HSA: s_getpc
define void @stack_12xv3i32() #0 { define void @stack_12xv3i32() #0 {
entry: entry:
call void @external_void_func_12xv3i32( call void @external_void_func_12xv3i32(
<3 x i32><i32 0, i32 0, i32 0>, <3 x i32><i32 0, i32 0, i32 0>,
<3 x i32><i32 1, i32 1, i32 1>, <3 x i32><i32 1, i32 1, i32 1>,
<3 x i32><i32 2, i32 2, i32 2>, <3 x i32><i32 2, i32 2, i32 2>,
<3 x i32><i32 3, i32 3, i32 3>, <3 x i32><i32 3, i32 3, i32 3>,
<3 x i32><i32 4, i32 4, i32 4>, <3 x i32><i32 4, i32 4, i32 4>,
<3 x i32><i32 5, i32 5, i32 5>, <3 x i32><i32 5, i32 5, i32 5>,
<3 x i32><i32 6, i32 6, i32 6>, <3 x i32><i32 6, i32 6, i32 6>,
<3 x i32><i32 7, i32 7, i32 7>, <3 x i32><i32 7, i32 7, i32 7>,
<3 x i32><i32 8, i32 8, i32 8>, <3 x i32><i32 8, i32 8, i32 8>,
<3 x i32><i32 9, i32 9, i32 9>, <3 x i32><i32 9, i32 9, i32 9>,
<3 x i32><i32 10, i32 11, i32 12>, <3 x i32><i32 10, i32 11, i32 12>,
<3 x i32><i32 13, i32 14, i32 15>) <3 x i32><i32 13, i32 14, i32 15>)
ret void ret void
} }
; GCN-LABEL: {{^}}stack_12xv3f32: ; GCN-LABEL: {{^}}stack_12xv3f32:
; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000 ; MESA: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
; GCN: buffer_store_dword [[REG12]], {{.*$}} ; MESA: buffer_store_dword [[REG12]], {{.*$}}
; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000 ; MESA: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
; GCN: buffer_store_dword [[REG13]], {{.*}} offset:4 ; MESA: buffer_store_dword [[REG13]], {{.*}} offset:4
; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000 ; MESA: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
; GCN: buffer_store_dword [[REG14]], {{.*}} offset:8 ; MESA: buffer_store_dword [[REG14]], {{.*}} offset:8
; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000 ; MESA: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
; GCN: buffer_store_dword [[REG15]], {{.*}} offset:12 ; MESA: buffer_store_dword [[REG15]], {{.*}} offset:12
; GCN: v_mov_b32_e32 v31, 0x41300000 ; MESA: v_mov_b32_e32 v31, 0x41300000
; GCN: s_getpc ; MESA: s_getpc
; HSA: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
; HSA: buffer_store_dword [[REG12]], {{.*}} offset:4
; HSA: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
; HSA: buffer_store_dword [[REG13]], {{.*}} offset:8
; HSA: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
; HSA: buffer_store_dword [[REG14]], {{.*}} offset:12
; HSA: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
; HSA: buffer_store_dword [[REG15]], {{.*}} offset:16
; HSA: s_getpc
define void @stack_12xv3f32() #0 { define void @stack_12xv3f32() #0 {
entry: entry:
call void @external_void_func_12xv3f32( call void @external_void_func_12xv3f32(
<3 x float><float 0.0, float 0.0, float 0.0>, <3 x float><float 0.0, float 0.0, float 0.0>,
<3 x float><float 1.0, float 1.0, float 1.0>, <3 x float><float 1.0, float 1.0, float 1.0>,
<3 x float><float 2.0, float 2.0, float 2.0>, <3 x float><float 2.0, float 2.0, float 2.0>,
<3 x float><float 3.0, float 3.0, float 3.0>, <3 x float><float 3.0, float 3.0, float 3.0>,
<3 x float><float 4.0, float 4.0, float 4.0>, <3 x float><float 4.0, float 4.0, float 4.0>,
<3 x float><float 5.0, float 5.0, float 5.0>, <3 x float><float 5.0, float 5.0, float 5.0>,
<3 x float><float 6.0, float 6.0, float 6.0>, <3 x float><float 6.0, float 6.0, float 6.0>,
<3 x float><float 7.0, float 7.0, float 7.0>, <3 x float><float 7.0, float 7.0, float 7.0>,
<3 x float><float 8.0, float 8.0, float 8.0>, <3 x float><float 8.0, float 8.0, float 8.0>,
<3 x float><float 9.0, float 9.0, float 9.0>, <3 x float><float 9.0, float 9.0, float 9.0>,
<3 x float><float 10.0, float 11.0, float 12.0>, <3 x float><float 10.0, float 11.0, float 12.0>,
<3 x float><float 13.0, float 14.0, float 15.0>) <3 x float><float 13.0, float 14.0, float 15.0>)
ret void ret void
} }
; GCN-LABEL: {{^}}stack_8xv5i32: ; GCN-LABEL: {{^}}stack_8xv5i32:
; GCN: v_mov_b32_e32 [[REG8:v[0-9]+]], 8 ; MESA: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
; GCN: buffer_store_dword [[REG8]], {{.*$}} ; MESA: buffer_store_dword [[REG8]], {{.*$}}
; GCN: v_mov_b32_e32 [[REG9:v[0-9]+]], 9 ; MESA: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
; GCN: buffer_store_dword [[REG9]], {{.*}} offset:4 ; MESA: buffer_store_dword [[REG9]], {{.*}} offset:4
; GCN: v_mov_b32_e32 [[REG10:v[0-9]+]], 10 ; MESA: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
; GCN: buffer_store_dword [[REG10]], {{.*}} offset:8 ; MESA: buffer_store_dword [[REG10]], {{.*}} offset:8
; GCN: v_mov_b32_e32 [[REG11:v[0-9]+]], 11 ; MESA: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
; GCN: buffer_store_dword [[REG11]], {{.*}} offset:12 ; MESA: buffer_store_dword [[REG11]], {{.*}} offset:12
; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 12 ; MESA: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
; GCN: buffer_store_dword [[REG12]], {{.*}} offset:16 ; MESA: buffer_store_dword [[REG12]], {{.*}} offset:16
; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 13 ; MESA: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
; GCN: buffer_store_dword [[REG13]], {{.*}} offset:20 ; MESA: buffer_store_dword [[REG13]], {{.*}} offset:20
; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 14 ; MESA: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
; GCN: buffer_store_dword [[REG14]], {{.*}} offset:24 ; MESA: buffer_store_dword [[REG14]], {{.*}} offset:24
; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 15 ; MESA: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
; GCN: buffer_store_dword [[REG15]], {{.*}} offset:28 ; MESA: buffer_store_dword [[REG15]], {{.*}} offset:28
; HSA: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
; HSA: buffer_store_dword [[REG8]], {{.*}} offset:4
; HSA: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
; HSA: buffer_store_dword [[REG9]], {{.*}} offset:8
; HSA: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
; HSA: buffer_store_dword [[REG10]], {{.*}} offset:12
; HSA: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
; HSA: buffer_store_dword [[REG11]], {{.*}} offset:16
; HSA: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
; HSA: buffer_store_dword [[REG12]], {{.*}} offset:20
; HSA: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
; HSA: buffer_store_dword [[REG13]], {{.*}} offset:24
; HSA: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
; HSA: buffer_store_dword [[REG14]], {{.*}} offset:28
; HSA: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
; HSA: buffer_store_dword [[REG15]], {{.*}} offset:32
; GCN: v_mov_b32_e32 v31, 7
; MESA: v_mov_b32_e32 v31, 7
; GCN: s_getpc ; GCN: s_getpc
define void @stack_8xv5i32() #0 { define void @stack_8xv5i32() #0 {
entry: entry:
call void @external_void_func_8xv5i32( call void @external_void_func_8xv5i32(
<5 x i32><i32 0, i32 0, i32 0, i32 0, i32 0>, <5 x i32><i32 0, i32 0, i32 0, i32 0, i32 0>,
<5 x i32><i32 1, i32 1, i32 1, i32 1, i32 1>, <5 x i32><i32 1, i32 1, i32 1, i32 1, i32 1>,
<5 x i32><i32 2, i32 2, i32 2, i32 2, i32 2>, <5 x i32><i32 2, i32 2, i32 2, i32 2, i32 2>,
<5 x i32><i32 3, i32 3, i32 3, i32 3, i32 3>, <5 x i32><i32 3, i32 3, i32 3, i32 3, i32 3>,
<5 x i32><i32 4, i32 4, i32 4, i32 4, i32 4>, <5 x i32><i32 4, i32 4, i32 4, i32 4, i32 4>,
<5 x i32><i32 5, i32 5, i32 5, i32 5, i32 5>, <5 x i32><i32 5, i32 5, i32 5, i32 5, i32 5>,
<5 x i32><i32 6, i32 7, i32 8, i32 9, i32 10>, <5 x i32><i32 6, i32 7, i32 8, i32 9, i32 10>,
<5 x i32><i32 11, i32 12, i32 13, i32 14, i32 15>) <5 x i32><i32 11, i32 12, i32 13, i32 14, i32 15>)
ret void ret void
} }
; GCN-LABEL: {{^}}stack_8xv5f32: ; GCN-LABEL: {{^}}stack_8xv5f32:
; GCN: v_mov_b32_e32 [[REG8:v[0-9]+]], 0x41000000 ; MESA: v_mov_b32_e32 [[REG8:v[0-9]+]], 0x41000000
; GCN: buffer_store_dword [[REG8]], {{.*$}} ; MESA: buffer_store_dword [[REG8]], {{.*$}}
; GCN: v_mov_b32_e32 [[REG9:v[0-9]+]], 0x41100000 ; MESA: v_mov_b32_e32 [[REG9:v[0-9]+]], 0x41100000
; GCN: buffer_store_dword [[REG9]], {{.*}} offset:4 ; MESA: buffer_store_dword [[REG9]], {{.*}} offset:4
; GCN: v_mov_b32_e32 [[REG10:v[0-9]+]], 0x41200000 ; MESA: v_mov_b32_e32 [[REG10:v[0-9]+]], 0x41200000
; GCN: buffer_store_dword [[REG10]], {{.*}} offset:8 ; MESA: buffer_store_dword [[REG10]], {{.*}} offset:8
; GCN: v_mov_b32_e32 [[REG11:v[0-9]+]], 0x41300000 ; MESA: v_mov_b32_e32 [[REG11:v[0-9]+]], 0x41300000
; GCN: buffer_store_dword [[REG11]], {{.*}} offset:12 ; MESA: buffer_store_dword [[REG11]], {{.*}} offset:12
; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000 ; MESA: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
; GCN: buffer_store_dword [[REG12]], {{.*}} offset:16 ; MESA: buffer_store_dword [[REG12]], {{.*}} offset:16
; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000 ; MESA: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
; GCN: buffer_store_dword [[REG13]], {{.*}} offset:20 ; MESA: buffer_store_dword [[REG13]], {{.*}} offset:20
; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000 ; MESA: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
; GCN: buffer_store_dword [[REG14]], {{.*}} offset:24 ; MESA: buffer_store_dword [[REG14]], {{.*}} offset:24
; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000 ; MESA: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
; GCN: buffer_store_dword [[REG15]], {{.*}} offset:28 ; MESA: buffer_store_dword [[REG15]], {{.*}} offset:28
; MESA: v_mov_b32_e32 v31, 0x40e00000
; GCN: v_mov_b32_e32 v31, 0x40e00000
; HSA: v_mov_b32_e32 [[REG8:v[0-9]+]], 0x40e00000
; HSA: buffer_store_dword [[REG8]], {{.*$}}
; HSA: v_mov_b32_e32 [[REG8:v[0-9]+]], 0x41000000
; HSA: buffer_store_dword [[REG8]], {{.*}} offset:4
; HSA: v_mov_b32_e32 [[REG9:v[0-9]+]], 0x41100000
; HSA: buffer_store_dword [[REG9]], {{.*}} offset:8
; HSA: v_mov_b32_e32 [[REG10:v[0-9]+]], 0x41200000
; HSA: buffer_store_dword [[REG10]], {{.*}} offset:12
; HSA: v_mov_b32_e32 [[REG11:v[0-9]+]], 0x41300000
; HSA: buffer_store_dword [[REG11]], {{.*}} offset:16
; HSA: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
; HSA: buffer_store_dword [[REG12]], {{.*}} offset:20
; HSA: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
; HSA: buffer_store_dword [[REG13]], {{.*}} offset:24
; HSA: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
; HSA: buffer_store_dword [[REG14]], {{.*}} offset:28
; HSA: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
; HSA: buffer_store_dword [[REG15]], {{.*}} offset:32
; GCN: s_getpc ; GCN: s_getpc
define void @stack_8xv5f32() #0 { define void @stack_8xv5f32() #0 {
entry: entry:
call void @external_void_func_8xv5f32( call void @external_void_func_8xv5f32(
<5 x float><float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>, <5 x float><float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>,
<5 x float><float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, <5 x float><float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>,
<5 x float><float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>, <5 x float><float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>,
<5 x float><float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>, <5 x float><float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>,
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