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llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
| Show First 20 Lines • Show All 409 Lines • ▼ Show 20 Lines | #endif | ||||
| if (!forceUnitLatencies()) { | if (!forceUnitLatencies()) { | ||||
| // Updating predecessor's height. This is now the cycle when the | // Updating predecessor's height. This is now the cycle when the | ||||
| // predecessor can be scheduled without causing a pipeline stall. | // predecessor can be scheduled without causing a pipeline stall. | ||||
| PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); | PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); | ||||
| } | } | ||||
| // If all the node's successors are scheduled, this node is ready | // If all the node's successors are scheduled, this node is ready | ||||
| // to be scheduled. Ignore the special EntrySU node. | // to be scheduled. | ||||
| if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) { | if (PredSU->NumSuccsLeft == 0) { | ||||
| PredSU->isAvailable = true; | PredSU->isAvailable = true; | ||||
| unsigned Height = PredSU->getHeight(); | unsigned Height = PredSU->getHeight(); | ||||
| if (Height < MinAvailableCycle) | if (Height < MinAvailableCycle) | ||||
| MinAvailableCycle = Height; | MinAvailableCycle = Height; | ||||
| if (isReady(PredSU)) { | if (isReady(PredSU)) { | ||||
| AvailableQueue->push(PredSU); | AvailableQueue->push(PredSU); | ||||
| ▲ Show 20 Lines • Show All 2,764 Lines • Show Last 20 Lines | |||||