Page MenuHomePhabricator
Differential D87867 Diff 292647 llvm/lib/CodeGen/MachineScheduler.cpp

Changeset View

Standalone View

View Options

llvm/lib/CodeGen/MachineScheduler.cpp

Show First 20 Lines • Show All 674 Lines • ▼ Show 20 Lines#ifndef NDEBUG
} }
#endif #endif
// SU->BotReadyCycle was set to CurrCycle when it was scheduled. However, // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
// CurrCycle may have advanced since then. // CurrCycle may have advanced since then.
if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
--PredSU->NumSuccsLeft; --PredSU->NumSuccsLeft;
if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) if (PredSU->NumSuccsLeft == 0)
SchedImpl->releaseBottomNode(PredSU); SchedImpl->releaseBottomNode(PredSU);
} }
/// releasePredecessors - Call releasePred on each of SU's predecessors. /// releasePredecessors - Call releasePred on each of SU's predecessors.
void ScheduleDAGMI::releasePredecessors(SUnit *SU) { void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
for (SDep &Pred : SU->Preds) for (SDep &Pred : SU->Preds)
releasePred(SU, &Pred); releasePred(SU, &Pred);
} }
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
} }
/// Identify DAG roots and setup scheduler queues. /// Identify DAG roots and setup scheduler queues.
void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots, void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
ArrayRef<SUnit*> BotRoots) { ArrayRef<SUnit*> BotRoots) {
NextClusterSucc = nullptr; NextClusterSucc = nullptr;
NextClusterPred = nullptr; NextClusterPred = nullptr;
// Release all DAG roots for scheduling, not including EntrySU/ExitSU. // Release all DAG roots for scheduling, not including ExitSU.
// //
// Nodes with unreleased weak edges can still be roots. // Nodes with unreleased weak edges can still be roots.
// Release top roots in forward order. // Release top roots in forward order.
for (SUnit *SU : TopRoots) for (SUnit *SU : TopRoots)
SchedImpl->releaseTopNode(SU); SchedImpl->releaseTopNode(SU);
// Release bottom roots in reverse order so the higher priority nodes appear // Release bottom roots in reverse order so the higher priority nodes appear
// first. This is more natural and slightly more efficient. // first. This is more natural and slightly more efficient.
for (SmallVectorImpl<SUnit*>::const_reverse_iterator for (SmallVectorImpl<SUnit*>::const_reverse_iterator
I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) { I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
SchedImpl->releaseBottomNode(*I); SchedImpl->releaseBottomNode(*I);
} }
releaseSuccessors(&EntrySU);
releasePredecessors(&ExitSU); releasePredecessors(&ExitSU);
SchedImpl->registerRoots(); SchedImpl->registerRoots();
// Advance past initial DebugValues. // Advance past initial DebugValues.
CurrentTop = nextIfDebug(RegionBegin, RegionEnd); CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
CurrentBottom = RegionEnd; CurrentBottom = RegionEnd;
} }
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines if (ShouldTrackLaneMasks) {
} }
} }
} }
} }
} }
void ScheduleDAGMILive::dump() const { void ScheduleDAGMILive::dump() const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
if (EntrySU.getInstr() != nullptr)
dumpNodeAll(EntrySU);
for (const SUnit &SU : SUnits) { for (const SUnit &SU : SUnits) {
dumpNodeAll(SU); dumpNodeAll(SU);
if (ShouldTrackPressure) { if (ShouldTrackPressure) {
dbgs() << " Pressure Diff : "; dbgs() << " Pressure Diff : ";
getPressureDiff(&SU).dump(*TRI); getPressureDiff(&SU).dump(*TRI);
} }
dbgs() << " Single Issue : "; dbgs() << " Single Issue : ";
if (SchedModel.mustBeginGroup(SU.getInstr()) && if (SchedModel.mustBeginGroup(SU.getInstr()) &&
▲ Show 20 Lines • Show All 2,667 Lines • Show Last 20 Lines