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llvm/include/llvm/CodeGen/ScheduleDAG.h
| Show First 20 Lines • Show All 554 Lines • ▼ Show 20 Lines | class TargetRegisterInfo; | ||||
| class ScheduleDAG { | class ScheduleDAG { | ||||
| public: | public: | ||||
| const LLVMTargetMachine &TM; ///< Target processor | const LLVMTargetMachine &TM; ///< Target processor | ||||
| const TargetInstrInfo *TII; ///< Target instruction information | const TargetInstrInfo *TII; ///< Target instruction information | ||||
| const TargetRegisterInfo *TRI; ///< Target processor register info | const TargetRegisterInfo *TRI; ///< Target processor register info | ||||
| MachineFunction &MF; ///< Machine function | MachineFunction &MF; ///< Machine function | ||||
| MachineRegisterInfo &MRI; ///< Virtual/real register map | MachineRegisterInfo &MRI; ///< Virtual/real register map | ||||
| std::vector<SUnit> SUnits; ///< The scheduling units. | std::vector<SUnit> SUnits; ///< The scheduling units. | ||||
| SUnit EntrySU; ///< Special node for the region entry. | |||||
| SUnit ExitSU; ///< Special node for the region exit. | SUnit ExitSU; ///< Special node for the region exit. | ||||
| #ifdef NDEBUG | #ifdef NDEBUG | ||||
| static const bool StressSched = false; | static const bool StressSched = false; | ||||
| #else | #else | ||||
| bool StressSched; | bool StressSched; | ||||
| #endif | #endif | ||||
| ▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines | |||||