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llvm/lib/Target/VE/VEInstrInfo.td
| Show First 20 Lines • Show All 892 Lines • ▼ Show 20 Lines | |||||
| // Assembly Language Reference Manual. | // Assembly Language Reference Manual. | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| //----------------------------------------------------------------------------- | //----------------------------------------------------------------------------- | ||||
| // Section 8.2 - Load/Store instructions | // Section 8.2 - Load/Store instructions | ||||
| //----------------------------------------------------------------------------- | //----------------------------------------------------------------------------- | ||||
| // Multiclass for generic RM instructions | // Multiclass for generic RM instructions | ||||
| multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC> { | multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC> { | ||||
simoll: unrelated change | |||||
Thanks. I'll remove this. kaz7: Thanks. I'll remove this. | |||||
| def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr), | def rri : RM<opc, (outs RC:$dest), (ins MEMrri:$addr), | ||||
| !strconcat(opcStr, " $dest, $addr"), []>; | !strconcat(opcStr, " $dest, $addr"), []>; | ||||
| let cy = 0 in | let cy = 0 in | ||||
| def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr), | def rii : RM<opc, (outs RC:$dest), (ins MEMrii:$addr), | ||||
| !strconcat(opcStr, " $dest, $addr"), []>; | !strconcat(opcStr, " $dest, $addr"), []>; | ||||
| let cz = 0 in | let cz = 0 in | ||||
| def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr), | def zri : RM<opc, (outs RC:$dest), (ins MEMzri:$addr), | ||||
| !strconcat(opcStr, " $dest, $addr"), []>; | !strconcat(opcStr, " $dest, $addr"), []>; | ||||
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| defm LD2BZX : LOADm<"ld2b.zx", 0x04, I32, i32, zextloadi16>; | defm LD2BZX : LOADm<"ld2b.zx", 0x04, I32, i32, zextloadi16>; | ||||
| // Section 8.2.6 - LD1B | // Section 8.2.6 - LD1B | ||||
| let DecoderMethod = "DecodeLoadI32" in | let DecoderMethod = "DecodeLoadI32" in | ||||
| defm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>; | defm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>; | ||||
| let cx = 1, DecoderMethod = "DecodeLoadI32" in | let cx = 1, DecoderMethod = "DecodeLoadI32" in | ||||
| defm LD1BZX : LOADm<"ld1b.zx", 0x05, I32, i32, zextloadi8>; | defm LD1BZX : LOADm<"ld1b.zx", 0x05, I32, i32, zextloadi8>; | ||||
| // LDQ pseudo instructions | |||||
| let mayLoad = 1, hasSideEffects = 0 in { | |||||
| def LDQrii : Pseudo<(outs F128:$dest), (ins MEMrii:$addr), | |||||
| "# pseudo ldq $dest, $addr", | |||||
| [(set f128:$dest, (load ADDRrii:$addr))]>; | |||||
| } | |||||
| // Multiclass for store instructions. | // Multiclass for store instructions. | ||||
| let mayStore = 1 in | let mayStore = 1 in | ||||
| multiclass STOREm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty, | multiclass STOREm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty, | ||||
| SDPatternOperator OpNode = null_frag> { | SDPatternOperator OpNode = null_frag> { | ||||
| def rri : RM<opc, (outs), (ins MEMrri:$addr, RC:$sx), | def rri : RM<opc, (outs), (ins MEMrri:$addr, RC:$sx), | ||||
| !strconcat(opcStr, " $sx, $addr"), | !strconcat(opcStr, " $sx, $addr"), | ||||
| [(OpNode Ty:$sx, ADDRrri:$addr)]>; | [(OpNode Ty:$sx, ADDRrri:$addr)]>; | ||||
| let cy = 0 in | let cy = 0 in | ||||
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| // Section 8.2.10 - ST2B | // Section 8.2.10 - ST2B | ||||
| let DecoderMethod = "DecodeStoreI32" in | let DecoderMethod = "DecodeStoreI32" in | ||||
| defm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>; | defm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>; | ||||
| // Section 8.2.11 - ST1B | // Section 8.2.11 - ST1B | ||||
| let DecoderMethod = "DecodeStoreI32" in | let DecoderMethod = "DecodeStoreI32" in | ||||
| defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>; | defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>; | ||||
| // STQ pseudo instructions | |||||
| let mayStore = 1, hasSideEffects = 0 in { | |||||
| def STQrii : Pseudo<(outs), (ins MEMrii:$addr, F128:$sx), | |||||
| "# pseudo stq $sx, $addr", | |||||
| [(store f128:$sx, ADDRrii:$addr)]>; | |||||
| } | |||||
| // Section 8.2.12 - DLDS | // Section 8.2.12 - DLDS | ||||
| let DecoderMethod = "DecodeLoadI64" in | let DecoderMethod = "DecodeLoadI64" in | ||||
| defm DLD : LOADm<"dld", 0x09, I64, i64, load>; | defm DLD : LOADm<"dld", 0x09, I64, i64, load>; | ||||
| // Section 8.2.13 - DLDU | // Section 8.2.13 - DLDU | ||||
| let DecoderMethod = "DecodeLoadF32" in | let DecoderMethod = "DecodeLoadF32" in | ||||
| defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>; | defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>; | ||||
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| let cw = 0, cx = 1 in | let cw = 0, cx = 1 in | ||||
| defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>; | defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>; | ||||
| let cw = 1, cx = 0 in | let cw = 1, cx = 0 in | ||||
| defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>; | defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>; | ||||
| let cw = 1, cx = 1 in | let cw = 1, cx = 1 in | ||||
| defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>; | defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>; | ||||
| // Section 8.7.7 - FAQ (Floating Add Quadruple) | // Section 8.7.7 - FAQ (Floating Add Quadruple) | ||||
| defm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128>; | defm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128, fadd>; | ||||
| // Section 8.7.8 - FSQ (Floating Subtract Quadruple) | // Section 8.7.8 - FSQ (Floating Subtract Quadruple) | ||||
| defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128>; | defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128, fsub>; | ||||
| // Section 8.7.9 - FMQ (Floating Subtract Quadruple) | // Section 8.7.9 - FMQ (Floating Subtract Quadruple) | ||||
| defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128>; | defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128, fmul>; | ||||
| // Section 8.7.10 - FCQ (Floating Compare Quadruple) | // Section 8.7.10 - FCQ (Floating Compare Quadruple) | ||||
| defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp, | defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp, | ||||
| mimmfp>; | mimmfp>; | ||||
| // Section 8.7.11 - FIX (Convert to Fixed Point) | // Section 8.7.11 - FIX (Convert to Fixed Point) | ||||
| // cx: double/float, cw: sx/zx, sz{0-3} = round | // cx: double/float, cw: sx/zx, sz{0-3} = round | ||||
| let cx = 0, cw = 0 /* sign extend */ in | let cx = 0, cw = 0 /* sign extend */ in | ||||
| ▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Lines | multiclass TRUNC64m<SDPatternOperator from, | ||||
| def : Pat<(from i64:$src, ADDRzii:$addr), | def : Pat<(from i64:$src, ADDRzii:$addr), | ||||
| (tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; | (tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>; | ||||
| } | } | ||||
| defm : TRUNC64m<truncstorei8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>; | defm : TRUNC64m<truncstorei8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>; | ||||
| defm : TRUNC64m<truncstorei16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>; | defm : TRUNC64m<truncstorei16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>; | ||||
| defm : TRUNC64m<truncstorei32, STLrri, STLrii, STLzri, ST1Bzii>; | defm : TRUNC64m<truncstorei32, STLrri, STLrii, STLzri, ST1Bzii>; | ||||
| // Address calculation and its optimization | // Address calculation and its optimization | ||||
| def : Pat<(VEhi tconstpool:$in), (LEASLzii 0, 0, tconstpool:$in)>; | |||||
| def : Pat<(VElo tconstpool:$in), | |||||
| (ANDrm (LEAzii 0, 0, tconstpool:$in), !add(32, 64))>; | |||||
| def : Pat<(add (VEhi tconstpool:$in1), (VElo tconstpool:$in2)), | |||||
| (LEASLrii (ANDrm (LEAzii 0, 0, tconstpool:$in2), !add(32, 64)), 0, | |||||
| (tconstpool:$in1))>; | |||||
| // Address calculation and its optimization | |||||
| def : Pat<(VEhi tglobaladdr:$in), (LEASLzii 0, 0, tglobaladdr:$in)>; | def : Pat<(VEhi tglobaladdr:$in), (LEASLzii 0, 0, tglobaladdr:$in)>; | ||||
| def : Pat<(VElo tglobaladdr:$in), | def : Pat<(VElo tglobaladdr:$in), | ||||
| (ANDrm (LEAzii 0, 0, tglobaladdr:$in), !add(32, 64))>; | (ANDrm (LEAzii 0, 0, tglobaladdr:$in), !add(32, 64))>; | ||||
| def : Pat<(add (VEhi tglobaladdr:$in1), (VElo tglobaladdr:$in2)), | def : Pat<(add (VEhi tglobaladdr:$in1), (VElo tglobaladdr:$in2)), | ||||
| (LEASLrii (ANDrm (LEAzii 0, 0, tglobaladdr:$in2), !add(32, 64)), 0, | (LEASLrii (ANDrm (LEAzii 0, 0, tglobaladdr:$in2), !add(32, 64)), 0, | ||||
| (tglobaladdr:$in1))>; | (tglobaladdr:$in1))>; | ||||
| // GlobalTLS address calculation and its optimization | // GlobalTLS address calculation and its optimization | ||||
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unrelated change