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Differential D86035 Diff 285934 llvm/lib/Target/VE/VEInstrInfo.cpp

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llvm/lib/Target/VE/VEInstrInfo.cpp

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Linesbool VEInstrInfo::reverseBranchCondition(
return false; return false;
} }
static bool IsAliasOfSX(Register Reg) { static bool IsAliasOfSX(Register Reg) {
return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
VE::F32RegClass.contains(Reg); VE::F32RegClass.contains(Reg);
} }
static void copyPhysSubRegs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, const DebugLoc &DL,
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
const MCInstrDesc &MCID, unsigned int NumSubRegs,
const unsigned *SubRegIdx,
const TargetRegisterInfo *TRI) {
MachineInstr *MovMI = nullptr;
for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) {
Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]);
Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]);
assert(SubDest && SubSrc && "Bad sub-register");
if (MCID.getOpcode() == VE::ORri) {
// generate "ORri, dest, src, 0" instruction.
MachineInstrBuilder MIB =
BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
MovMI = MIB.getInstr();
} else {
llvm_unreachable("Unexpected reg-to-reg copy instruction");
}
}
// Add implicit super-register defs and kills to the last MovMI.
MovMI->addRegisterDefined(DestReg, TRI);
if (KillSrc)
MovMI->addRegisterKilled(SrcReg, TRI, true);
}
void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, const DebugLoc &DL, MachineBasicBlock::iterator I, const DebugLoc &DL,
MCRegister DestReg, MCRegister SrcReg, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const { bool KillSrc) const {
if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
BuildMI(MBB, I, DL, get(VE::ORri), DestReg) BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0); .addImm(0);
} else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
// Use two instructions.
const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
unsigned int NumSubRegs = 2;
copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri),
NumSubRegs, SubRegIdx, &getRegisterInfo());
} else { } else {
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo();
dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI) dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI)
<< " to " << printReg(DestReg, TRI) << "\n"; << " to " << printReg(DestReg, TRI) << "\n";
llvm_unreachable("Impossible reg-to-reg copy"); llvm_unreachable("Impossible reg-to-reg copy");
} }
} }
/// isLoadFromStackSlot - If the specified machine instruction is a direct /// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of /// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If /// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot. /// any side effects other than loading from the stack slot.
unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const { int &FrameIndex) const {
if (MI.getOpcode() == VE::LDrii || // I64 if (MI.getOpcode() == VE::LDrii || // I64
MI.getOpcode() == VE::LDLSXrii || // I32 MI.getOpcode() == VE::LDLSXrii || // I32
MI.getOpcode() == VE::LDUrii // F32 MI.getOpcode() == VE::LDUrii || // F32
MI.getOpcode() == VE::LDQrii // F128 (pseudo)
) { ) {
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() && MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() &&
MI.getOperand(3).getImm() == 0) { MI.getOperand(3).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex(); FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg(); return MI.getOperand(0).getReg();
} }
} }
return 0; return 0;
} }
/// isStoreToStackSlot - If the specified machine instruction is a direct /// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of /// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If /// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot. /// any side effects other than storing to the stack slot.
unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const { int &FrameIndex) const {
if (MI.getOpcode() == VE::STrii || // I64 if (MI.getOpcode() == VE::STrii || // I64
MI.getOpcode() == VE::STLrii || // I32 MI.getOpcode() == VE::STLrii || // I32
MI.getOpcode() == VE::STUrii // F32 MI.getOpcode() == VE::STUrii || // F32
MI.getOpcode() == VE::STQrii // F128 (pseudo)
) { ) {
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() && MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) { MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex(); FrameIndex = MI.getOperand(0).getIndex();
return MI.getOperand(3).getReg(); return MI.getOperand(3).getReg();
} }
} }
Show All 32 Lines BuildMI(MBB, I, DL, get(VE::STLrii))
.addMemOperand(MMO); .addMemOperand(MMO);
} else if (RC == &VE::F32RegClass) { } else if (RC == &VE::F32RegClass) {
BuildMI(MBB, I, DL, get(VE::STUrii)) BuildMI(MBB, I, DL, get(VE::STUrii))
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
.addImm(0) .addImm(0)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO); .addMemOperand(MMO);
} else if (VE::F128RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(VE::STQrii))
.addFrameIndex(FI)
.addImm(0)
.addImm(0)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO);
} else } else
report_fatal_error("Can't store this register to stack slot"); report_fatal_error("Can't store this register to stack slot");
} }
void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
Register DestReg, int FI, Register DestReg, int FI,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
Show All 21 Lines BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg)
.addImm(0) .addImm(0)
.addMemOperand(MMO); .addMemOperand(MMO);
} else if (RC == &VE::F32RegClass) { } else if (RC == &VE::F32RegClass) {
BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg)
.addFrameIndex(FI) .addFrameIndex(FI)
.addImm(0) .addImm(0)
.addImm(0) .addImm(0)
.addMemOperand(MMO); .addMemOperand(MMO);
} else if (VE::F128RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg)
.addFrameIndex(FI)
.addImm(0)
.addImm(0)
.addMemOperand(MMO);
} else } else
report_fatal_error("Can't load this register from stack slot"); report_fatal_error("Can't load this register from stack slot");
} }
Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>(); VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>();
Register GlobalBaseReg = VEFI->getGlobalBaseReg(); Register GlobalBaseReg = VEFI->getGlobalBaseReg();
if (GlobalBaseReg != 0) if (GlobalBaseReg != 0)
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines