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llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
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; CHECK-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x7 = LD 32, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x7 = LD 32, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8) | ; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8) | ||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_64Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 | ; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_64Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 | ||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 | ; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 | ||||
; CHECKASM-LABEL: .test_byval_64Byte: | ; CHECKASM-LABEL: .test_byval_64Byte: | ||||
; ASM: stdu 1, -112(1) | ; ASM: stdu 1, -112(1) | ||||
; ASM-NEXT: ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2) | ; ASM-NEXT: ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2) | ||||
; ASM-DAG: ld 3, 0([[REG]]) | ; ASM-DAG: ld 3, 0([[REG]]) | ||||
; ASM-DAG: ld 4, 8([[REG]]) | ; ASM-DAG: ld 4, 8([[REG]]) | ||||
; ASM-DAG: ld 5, 16([[REG]]) | ; ASM-DAG: ld 5, 16([[REG]]) | ||||
; ASM-DAG: ld 6, 24([[REG]]) | ; ASM-DAG: ld 6, 24([[REG]]) | ||||
; ASM-DAG: ld 7, 32([[REG]]) | ; ASM-DAG: ld 7, 32([[REG]]) | ||||
; ASM-DAG: ld 8, 40([[REG]]) | ; ASM-DAG: ld 8, 40([[REG]]) | ||||
; ASM-DAG: ld 9, 48([[REG]]) | ; ASM-DAG: ld 9, 48([[REG]]) | ||||
; ASM-DAG: ld 10, 56([[REG]]) | ; ASM-DAG: ld 10, 56([[REG]]) | ||||
; ASM-NEXT: bl .test_byval_64Byte | ; ASM-NEXT: bl .test_byval_64Byte | ||||
; ASM-NEXT: nop | ; ASM-NEXT: nop |