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Differential D84765 Diff 283946 llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

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llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

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; CHECK-LABEL: name: caller ; CHECK-LABEL: name: caller
; 32BIT: liveins: ; 32BIT: liveins:
; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' } ; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' }
; 32BIT: body: | ; 32BIT: body: |
; 32BIT-NEXT: bb.0.entry: ; 32BIT-NEXT: bb.0.entry:
; 32BIT: liveins: $r3 ; 32BIT: liveins: $r3
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT: BL_NOP <mcsymbol .call_test_bool>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3 ; 32BIT: BL_NOP <mcsymbol .call_test_bool[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 64BIT: liveins: ; 64BIT: liveins:
; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' } ; 64BIT-NEXT: - { reg: '$x3', virtual-reg: '' }
; 64BIT: body: | ; 64BIT: body: |
; 64BIT-NEXT: bb.0.entry: ; 64BIT-NEXT: bb.0.entry:
; 64BIT-NEXT: liveins: $x3 ; 64BIT-NEXT: liveins: $x3
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT: BL8_NOP <mcsymbol .call_test_bool>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3 ; 64BIT: BL8_NOP <mcsymbol .call_test_bool[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
@f1 = global float 0.000000e+00, align 4 @f1 = global float 0.000000e+00, align 4
@d1 = global double 0.000000e+00, align 8 @d1 = global double 0.000000e+00, align 8
define void @call_test_floats() { define void @call_test_floats() {
entry: entry:
%0 = load float, float* @f1, align 4 %0 = load float, float* @f1, align 4
▲ Show 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8) ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8)
; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1) ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1)
; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4) ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8) ; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4) ; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_vararg: ; CHECKASM-LABEL: .call_test_vararg:
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stfd 1, 64(1) ; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfd 2, 72(1) ; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-DAG: lwz 4, 64(1) ; ASM32PWR4-DAG: lwz 4, 64(1)
; ASM32PWR4-DAG: lwz 5, 68(1) ; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 6, 72(1) ; ASM32PWR4-DAG: lwz 6, 72(1)
; ASM32PWR4-DAG: lwz 7, 76(1) ; ASM32PWR4-DAG: lwz 7, 76(1)
; ASM32PWR4-NEXT: bl .test_vararg ; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got) ; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1) ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]]) ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1) ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]]) ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]]) ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1) ; ASM64PWR4-NEXT: ld 4, 112(1)
; ASM64PWR4-NEXT: ld 5, 120(1) ; ASM64PWR4-NEXT: ld 5, 120(1)
; ASM64PWR4-NEXT: bl .test_vararg ; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
define void @call_test_vararg2() { define void @call_test_vararg2() {
entry: entry:
%0 = load float, float* @f1, align 4 %0 = load float, float* @f1, align 4
%conv = fpext float %0 to double %conv = fpext float %0 to double
%1 = load double, double* @d1, align 8 %1 = load double, double* @d1, align 8
call void (i32, ...) @test_vararg(i32 42, double %conv, i32 42, double %1) call void (i32, ...) @test_vararg(i32 42, double %conv, i32 42, double %1)
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; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1) ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d1)
; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4) ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8) ; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4) ; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 42 ; 32BIT-NEXT: $r6 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: li 6, 42 ; ASM32PWR4-NEXT: li 6, 42
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stfd 1, 64(1) ; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfd 2, 72(1) ; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-DAG: lwz 4, 64(1) ; ASM32PWR4-DAG: lwz 4, 64(1)
; ASM32PWR4-DAG: lwz 5, 68(1) ; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 7, 72(1) ; ASM32PWR4-DAG: lwz 7, 72(1)
; ASM32PWR4-DAG: lwz 8, 76(1) ; ASM32PWR4-DAG: lwz 8, 76(1)
; ASM32PWR4-NEXT: bl .test_vararg ; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got) ; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1) ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]]) ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1) ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]]) ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]]) ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: li 5, 42 ; ASM64PWR4-NEXT: li 5, 42
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1) ; ASM64PWR4-NEXT: ld 4, 112(1)
; ASM64PWR4-NEXT: ld 6, 120(1) ; ASM64PWR4-NEXT: ld 6, 120(1)
; ASM64PWR4-NEXT: bl .test_vararg ; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
define void @call_test_vararg3() { define void @call_test_vararg3() {
entry: entry:
%0 = load float, float* @f1, align 4 %0 = load float, float* @f1, align 4
%conv = fpext float %0 to double %conv = fpext float %0 to double
%1 = load double, double* @d1, align 8 %1 = load double, double* @d1, align 8
call void (i32, ...) @test_vararg(i32 42, double %conv, i64 42, double %1) call void (i32, ...) @test_vararg(i32 42, double %conv, i64 42, double %1)
Show All 11 Lines
; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4) ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 32BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8) ; 32BIT-NEXT: renamable $r8 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4) ; 32BIT-NEXT: renamable $r9 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 0 ; 32BIT-NEXT: $r6 = LI 0
; 32BIT-NEXT: $r7 = LI 42 ; 32BIT-NEXT: $r7 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-DAG: li 6, 0 ; ASM32PWR4-DAG: li 6, 0
; ASM32PWR4-DAG: li 7, 42 ; ASM32PWR4-DAG: li 7, 42
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stfd 1, 64(1) ; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfd 2, 72(1) ; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-DAG: lwz 4, 64(1) ; ASM32PWR4-DAG: lwz 4, 64(1)
; ASM32PWR4-DAG: lwz 5, 68(1) ; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 8, 72(1) ; ASM32PWR4-DAG: lwz 8, 72(1)
; ASM32PWR4-DAG: lwz 9, 76(1) ; ASM32PWR4-DAG: lwz 9, 76(1)
; ASM32PWR4-NEXT: bl .test_vararg ; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got) ; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1) ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]]) ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1) ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]]) ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]]) ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]]) ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: li 5, 42 ; ASM64PWR4-NEXT: li 5, 42
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-DAG: ld 4, 112(1) ; ASM64PWR4-DAG: ld 4, 112(1)
; ASM64PWR4-DAG: ld 6, 120(1) ; ASM64PWR4-DAG: ld 6, 120(1)
; ASM64PWR4-NEXT: bl .test_vararg ; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
define void @call_test_vararg4() { define void @call_test_vararg4() {
entry: entry:
%0 = load float, float* @f1, align 4 %0 = load float, float* @f1, align 4
call void (i32, ...) @test_vararg(i32 42, float %0) call void (i32, ...) @test_vararg(i32 42, float %0)
ret void ret void
} }
; CHECK-LABEL: name: call_test_vararg4 ; CHECK-LABEL: name: call_test_vararg4
; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load 4 from got) ; 32BIT: renamable $r[[REG:[0-9]+]] = LWZtoc @f1, $r2 :: (load 4 from got)
; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load 4 from @f1) ; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG]] :: (dereferenceable load 4 from @f1)
; 32BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]]) ; 32BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]]) ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -64(1) ; ASM32PWR4: stwu 1, -64(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfs 1, 60(1) ; ASM32PWR4-NEXT: stfs 1, 60(1)
; ASM32PWR4-NEXT: lwz 4, 60(1) ; ASM32PWR4-NEXT: lwz 4, 60(1)
; ASM32PWR4-NEXT: bl .test_vararg ; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got) ; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1) ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]]) ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]]) ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfs 1, 124(1) ; ASM64PWR4-NEXT: stfs 1, 124(1)
; ASM64PWR4-NEXT: lwz 4, 124(1) ; ASM64PWR4-NEXT: lwz 4, 124(1)
; ASM64PWR4-NEXT: bl .test_vararg ; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
@c = common global i8 0, align 1 @c = common global i8 0, align 1
@si = common global i16 0, align 2 @si = common global i16 0, align 2
@i = common global i32 0, align 4 @i = common global i32 0, align 4
@lli = common global i64 0, align 8 @lli = common global i64 0, align 8
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@d = common global double 0.000000e+00, align 8 @d = common global double 0.000000e+00, align 8
Show All 34 Lines
; 32BIT-DAG: renamable $r[[REGI:[0-9]+]] = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load 4 from @i) ; 32BIT-DAG: renamable $r[[REGI:[0-9]+]] = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load 4 from @i)
; 32BIT-DAG: STW killed renamable $r[[REGI]], 64, $r1 :: (store 4) ; 32BIT-DAG: STW killed renamable $r[[REGI]], 64, $r1 :: (store 4)
; 32BIT-DAG: renamable $r[[REGLLIADDR:[0-9]+]] = LWZtoc @lli, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGLLIADDR:[0-9]+]] = LWZtoc @lli, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $r[[REGLLI1:[0-9]+]] = LWZ 0, renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli, align 8) ; 32BIT-DAG: renamable $r[[REGLLI1:[0-9]+]] = LWZ 0, renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli, align 8)
; 32BIT-DAG: STW killed renamable $r[[REGLLI1]], 68, $r1 :: (store 4) ; 32BIT-DAG: STW killed renamable $r[[REGLLI1]], 68, $r1 :: (store 4)
; 32BIT-DAG: renamable $r[[REGLLI2:[0-9]+]] = LWZ 4, killed renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli + 4, align 8) ; 32BIT-DAG: renamable $r[[REGLLI2:[0-9]+]] = LWZ 4, killed renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REGLLI2]], 72, $r1 :: (store 4) ; 32BIT-DAG: STW killed renamable $r[[REGLLI2]], 72, $r1 :: (store 4)
; 32BIT-DAG: STW renamable $r[[REGI]], 76, $r1 :: (store 4) ; 32BIT-DAG: STW renamable $r[[REGI]], 76, $r1 :: (store 4)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_int: ; CHECKASM-LABEL: .call_test_stackarg_int:
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-DAG: li 3, 1 ; ASM32PWR4-DAG: li 3, 1
; ASM32PWR4-DAG: li 4, 2 ; ASM32PWR4-DAG: li 4, 2
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; ASM32PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]]) ; ASM32PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
; ASM32PWR4-DAG: stw [[REGI]], 64(1) ; ASM32PWR4-DAG: stw [[REGI]], 64(1)
; ASM32PWR4-DAG: lwz [[REGLLIADDR:[0-9]+]], L..C7(2) ; ASM32PWR4-DAG: lwz [[REGLLIADDR:[0-9]+]], L..C7(2)
; ASM32PWR4-DAG: lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]]) ; ASM32PWR4-DAG: lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]])
; ASM32PWR4-DAG: stw [[REGLLI1]], 68(1) ; ASM32PWR4-DAG: stw [[REGLLI1]], 68(1)
; ASM32PWR4-DAG: lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]]) ; ASM32PWR4-DAG: lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]])
; ASM32PWR4-DAG: stw [[REGLLI2]], 72(1) ; ASM32PWR4-DAG: stw [[REGLLI2]], 72(1)
; ASM32PWR4-DAG: stw [[REGI]], 76(1) ; ASM32PWR4-DAG: stw [[REGI]], 76(1)
; ASM32PWR4-NEXT: bl .test_stackarg_int ; ASM32PWR4-NEXT: bl .test_stackarg_int[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT-DAG: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-DAG: ADJCALLSTACKDOWN 152, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = LI8 1 ; 64BIT-DAG: $x3 = LI8 1
; 64BIT-DAG: $x4 = LI8 2 ; 64BIT-DAG: $x4 = LI8 2
; 64BIT-DAG: $x5 = LI8 3 ; 64BIT-DAG: $x5 = LI8 3
; 64BIT-DAG: $x6 = LI8 4 ; 64BIT-DAG: $x6 = LI8 4
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; 64BIT-DAG: STD killed renamable $x[[REGSI]], 120, $x1 :: (store 8) ; 64BIT-DAG: STD killed renamable $x[[REGSI]], 120, $x1 :: (store 8)
; 64BIT-DAG: renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i) ; 64BIT-DAG: renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i)
; 64BIT-DAG: STD killed renamable $x[[REGI]], 128, $x1 :: (store 8) ; 64BIT-DAG: STD killed renamable $x[[REGI]], 128, $x1 :: (store 8)
; 64BIT-DAG: renamable $x[[REGLLIADDR:[0-9]+]] = LDtoc @lli, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGLLIADDR:[0-9]+]] = LDtoc @lli, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli) ; 64BIT-DAG: renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli)
; 64BIT-DAG: STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8) ; 64BIT-DAG: STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8)
; 64BIT-DAG: STD renamable $x[[REGI]], 144, $x1 :: (store 8) ; 64BIT-DAG: STD renamable $x[[REGI]], 144, $x1 :: (store 8)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_int>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_int[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64PWR4-DAG: stdu 1, -160(1) ; ASM64PWR4-DAG: stdu 1, -160(1)
; ASM64PWR4-DAG: li 3, 1 ; ASM64PWR4-DAG: li 3, 1
; ASM64PWR4-DAG: li 4, 2 ; ASM64PWR4-DAG: li 4, 2
; ASM64PWR4-DAG: li 5, 3 ; ASM64PWR4-DAG: li 5, 3
; ASM64PWR4-DAG: li 6, 4 ; ASM64PWR4-DAG: li 6, 4
Show All 9 Lines
; ASM64PWR4-DAG: std [[REGSI]], 120(1) ; ASM64PWR4-DAG: std [[REGSI]], 120(1)
; ASM64PWR4-DAG: ld [[REGIADDR:[0-9]+]], L..C4(2) ; ASM64PWR4-DAG: ld [[REGIADDR:[0-9]+]], L..C4(2)
; ASM64PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]]) ; ASM64PWR4-DAG: lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
; ASM64PWR4-DAG: std [[REGI]], 128(1) ; ASM64PWR4-DAG: std [[REGI]], 128(1)
; ASM64PWR4-DAG: ld [[REGLLIADDR:[0-9]+]], L..C6(2) ; ASM64PWR4-DAG: ld [[REGLLIADDR:[0-9]+]], L..C6(2)
; ASM64PWR4-DAG: ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]]) ; ASM64PWR4-DAG: ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]])
; ASM64PWR4-DAG: std [[REGLLI]], 136(1) ; ASM64PWR4-DAG: std [[REGLLI]], 136(1)
; ASM64PWR4-DAG: std [[REGI]], 144(1) ; ASM64PWR4-DAG: std [[REGI]], 144(1)
; ASM64PWR4-NEXT: bl .test_stackarg_int ; ASM64PWR4-NEXT: bl .test_stackarg_int[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
; Basic saving of floating point type arguments to the parameter save area. ; Basic saving of floating point type arguments to the parameter save area.
; The float and double arguments will pass in both fpr as well as parameter save area. ; The float and double arguments will pass in both fpr as well as parameter save area.
define void @call_test_stackarg_float() { define void @call_test_stackarg_float() {
entry: entry:
%0 = load float, float* @f, align 4 %0 = load float, float* @f, align 4
%1 = load double, double* @d, align 8 %1 = load double, double* @d, align 8
Show All 16 Lines
; 32BIT-DAG: $r9 = LI 7 ; 32BIT-DAG: $r9 = LI 7
; 32BIT-DAG: $r10 = LI 8 ; 32BIT-DAG: $r10 = LI 8
; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $f1 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f) ; 32BIT-DAG: renamable $f1 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f)
; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d) ; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d)
; 32BIT-DAG: STFS renamable $f1, 56, $r1 :: (store 4) ; 32BIT-DAG: STFS renamable $f1, 56, $r1 :: (store 4)
; 32BIT-DAG: STFD renamable $f2, 60, $r1 :: (store 8) ; 32BIT-DAG: STFD renamable $f2, 60, $r1 :: (store 8)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float: ; CHECKASM-LABEL: .call_test_stackarg_float:
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-DAG: li 3, 1 ; ASM32PWR4-DAG: li 3, 1
; ASM32PWR4-DAG: li 4, 2 ; ASM32PWR4-DAG: li 4, 2
; ASM32PWR4-DAG: li 5, 3 ; ASM32PWR4-DAG: li 5, 3
; ASM32PWR4-DAG: li 6, 4 ; ASM32PWR4-DAG: li 6, 4
; ASM32PWR4-DAG: li 7, 5 ; ASM32PWR4-DAG: li 7, 5
; ASM32PWR4-DAG: li 8, 6 ; ASM32PWR4-DAG: li 8, 6
; ASM32PWR4-DAG: li 9, 7 ; ASM32PWR4-DAG: li 9, 7
; ASM32PWR4-DAG: li 10, 8 ; ASM32PWR4-DAG: li 10, 8
; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2) ; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2)
; ASM32PWR4-DAG: lfs 1, 0([[REGF]]) ; ASM32PWR4-DAG: lfs 1, 0([[REGF]])
; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2) ; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2)
; ASM32PWR4-DAG: lfd 2, 0([[REGD:[0-9]+]]) ; ASM32PWR4-DAG: lfd 2, 0([[REGD:[0-9]+]])
; ASM32PWR4-DAG: stfs 1, 56(1) ; ASM32PWR4-DAG: stfs 1, 56(1)
; ASM32PWR4-DAG: stfd 2, 60(1) ; ASM32PWR4-DAG: stfd 2, 60(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float ; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80 ; ASM32PWR4-NEXT: addi 1, 1, 80
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT-DAG: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-DAG: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = LI8 1 ; 64BIT-DAG: $x3 = LI8 1
; 64BIT-DAG: $x4 = LI8 2 ; 64BIT-DAG: $x4 = LI8 2
; 64BIT-DAG: $x5 = LI8 3 ; 64BIT-DAG: $x5 = LI8 3
; 64BIT-DAG: $x6 = LI8 4 ; 64BIT-DAG: $x6 = LI8 4
; 64BIT-DAG: $x7 = LI8 5 ; 64BIT-DAG: $x7 = LI8 5
; 64BIT-DAG: $x8 = LI8 6 ; 64BIT-DAG: $x8 = LI8 6
; 64BIT-DAG: $x9 = LI8 7 ; 64BIT-DAG: $x9 = LI8 7
; 64BIT-DAG: $x10 = LI8 8 ; 64BIT-DAG: $x10 = LI8 8
; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $f1 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f) ; 64BIT-DAG: renamable $f1 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d) ; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
; 64BIT-DAG: STFS renamable $f1, 112, $x1 :: (store 4) ; 64BIT-DAG: STFS renamable $f1, 112, $x1 :: (store 4)
; 64BIT-DAG: STFD renamable $f2, 120, $x1 :: (store 8) ; 64BIT-DAG: STFD renamable $f2, 120, $x1 :: (store 8)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-DAG: li 3, 1 ; ASM64PWR4-DAG: li 3, 1
; ASM64PWR4-DAG: li 4, 2 ; ASM64PWR4-DAG: li 4, 2
; ASM64PWR4-DAG: li 5, 3 ; ASM64PWR4-DAG: li 5, 3
; ASM64PWR4-DAG: li 6, 4 ; ASM64PWR4-DAG: li 6, 4
; ASM64PWR4-DAG: li 7, 5 ; ASM64PWR4-DAG: li 7, 5
; ASM64PWR4-DAG: li 8, 6 ; ASM64PWR4-DAG: li 8, 6
; ASM64PWR4-DAG: li 9, 7 ; ASM64PWR4-DAG: li 9, 7
; ASM64PWR4-DAG: li 10, 8 ; ASM64PWR4-DAG: li 10, 8
; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2) ; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2)
; ASM64PWR4-DAG: lfs 1, 0([[REGF]]) ; ASM64PWR4-DAG: lfs 1, 0([[REGF]])
; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2) ; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2)
; ASM64PWR4-DAG: lfd 2, 0([[REGD]]) ; ASM64PWR4-DAG: lfd 2, 0([[REGD]])
; ASM64PWR4-DAG: stfs 1, 112(1) ; ASM64PWR4-DAG: stfs 1, 112(1)
; ASM64PWR4-DAG: stfd 2, 120(1) ; ASM64PWR4-DAG: stfd 2, 120(1)
; ASM64PWR4-NEXT: bl .test_stackarg_float ; ASM64PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128 ; ASM64PWR4-NEXT: addi 1, 1, 128
define void @call_test_stackarg_float2() { define void @call_test_stackarg_float2() {
entry: entry:
%0 = load double, double* @d, align 8 %0 = load double, double* @d, align 8
call void (i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, double %0) call void (i32, i32, i32, i32, i32, i32, ...) @test_stackarg_float2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, double %0)
ret void ret void
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; 32BIT-DAG: $r6 = LI 4 ; 32BIT-DAG: $r6 = LI 4
; 32BIT-DAG: $r7 = LI 5 ; 32BIT-DAG: $r7 = LI 5
; 32BIT-DAG: $r8 = LI 6 ; 32BIT-DAG: $r8 = LI 6
; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d) ; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load 8 from @d)
; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 32BIT-DAG: renamable $r9 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8) ; 32BIT-DAG: renamable $r9 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
; 32BIT-DAG: renamable $r10 = LWZ 4, %stack.0 :: (load 4 from %stack.0 + 4) ; 32BIT-DAG: renamable $r10 = LWZ 4, %stack.0 :: (load 4 from %stack.0 + 4)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float2: ; CHECKASM-LABEL: .call_test_stackarg_float2:
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM32PWR4: stwu 1, -64(1) ; ASM32PWR4: stwu 1, -64(1)
; ASM32PWR4-DAG: li 3, 1 ; ASM32PWR4-DAG: li 3, 1
; ASM32PWR4-DAG: li 4, 2 ; ASM32PWR4-DAG: li 4, 2
; ASM32PWR4-DAG: li 5, 3 ; ASM32PWR4-DAG: li 5, 3
; ASM32PWR4-DAG: li 6, 4 ; ASM32PWR4-DAG: li 6, 4
; ASM32PWR4-DAG: li 7, 5 ; ASM32PWR4-DAG: li 7, 5
; ASM32PWR4-DAG: li 8, 6 ; ASM32PWR4-DAG: li 8, 6
; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2) ; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2)
; ASM32PWR4-DAG: lfd 1, 0([[REG]]) ; ASM32PWR4-DAG: lfd 1, 0([[REG]])
; ASM32PWR4-DAG: stfd 1, 56(1) ; ASM32PWR4-DAG: stfd 1, 56(1)
; ASM32PWR4-DAG: lwz 9, 56(1) ; ASM32PWR4-DAG: lwz 9, 56(1)
; ASM32PWR4-DAG: lwz 10, 60(1) ; ASM32PWR4-DAG: lwz 10, 60(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float2 ; ASM32PWR4-NEXT: bl .test_stackarg_float2[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 64 ; ASM32PWR4-NEXT: addi 1, 1, 64
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT-DAG: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-DAG: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = LI8 1 ; 64BIT-DAG: $x3 = LI8 1
; 64BIT-DAG: $x4 = LI8 2 ; 64BIT-DAG: $x4 = LI8 2
; 64BIT-DAG: $x5 = LI8 3 ; 64BIT-DAG: $x5 = LI8 3
; 64BIT-DAG: $x6 = LI8 4 ; 64BIT-DAG: $x6 = LI8 4
; 64BIT-DAG: $x7 = LI8 5 ; 64BIT-DAG: $x7 = LI8 5
; 64BIT-DAG: $x8 = LI8 6 ; 64BIT-DAG: $x8 = LI8 6
; 64BIT-DAG: renamable $x[[REG:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REG:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d) ; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d)
; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 64BIT-DAG: renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0) ; 64BIT-DAG: renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-DAG: li 3, 1 ; ASM64PWR4-DAG: li 3, 1
; ASM64PWR4-DAG: li 4, 2 ; ASM64PWR4-DAG: li 4, 2
; ASM64PWR4-DAG: li 5, 3 ; ASM64PWR4-DAG: li 5, 3
; ASM64PWR4-DAG: li 6, 4 ; ASM64PWR4-DAG: li 6, 4
; ASM64PWR4-DAG: li 7, 5 ; ASM64PWR4-DAG: li 7, 5
; ASM64PWR4-DAG: li 8, 6 ; ASM64PWR4-DAG: li 8, 6
; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2) ; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2)
; ASM64PWR4-DAG: lfd 1, 0([[REG]]) ; ASM64PWR4-DAG: lfd 1, 0([[REG]])
; ASM64PWR4-DAG: stfd 1, 120(1) ; ASM64PWR4-DAG: stfd 1, 120(1)
; ASM64PWR4-DAG: ld 9, 120(1) ; ASM64PWR4-DAG: ld 9, 120(1)
; ASM64PWR4-NEXT: bl .test_stackarg_float2 ; ASM64PWR4-NEXT: bl .test_stackarg_float2[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128 ; ASM64PWR4-NEXT: addi 1, 1, 128
; A double arg will pass on the stack in PPC32 if there is only one available GPR. ; A double arg will pass on the stack in PPC32 if there is only one available GPR.
define void @call_test_stackarg_float3() { define void @call_test_stackarg_float3() {
entry: entry:
%0 = load double, double* @d, align 8 %0 = load double, double* @d, align 8
%1 = load float, float* @f, align 4 %1 = load float, float* @f, align 4
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; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d) ; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d)
; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGF:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $f2 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f) ; 32BIT-DAG: renamable $f2 = LFS 0, killed renamable $r[[REGF]] :: (dereferenceable load 4 from @f)
; 32BIT-DAG: STFD renamable $f1, 52, $r1 :: (store 8) ; 32BIT-DAG: STFD renamable $f1, 52, $r1 :: (store 8)
; 32BIT-DAG: STFS renamable $f2, 60, $r1 :: (store 4) ; 32BIT-DAG: STFS renamable $f2, 60, $r1 :: (store 4)
; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 32BIT-DAG: renamable $r10 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8) ; 32BIT-DAG: renamable $r10 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float3: ; CHECKASM-LABEL: .call_test_stackarg_float3:
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-DAG: li 3, 1 ; ASM32PWR4-DAG: li 3, 1
; ASM32PWR4-DAG: li 4, 2 ; ASM32PWR4-DAG: li 4, 2
; ASM32PWR4-DAG: li 5, 3 ; ASM32PWR4-DAG: li 5, 3
; ASM32PWR4-DAG: li 6, 4 ; ASM32PWR4-DAG: li 6, 4
; ASM32PWR4-DAG: li 7, 5 ; ASM32PWR4-DAG: li 7, 5
; ASM32PWR4-DAG: li 8, 6 ; ASM32PWR4-DAG: li 8, 6
; ASM32PWR4-DAG: li 9, 7 ; ASM32PWR4-DAG: li 9, 7
; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2) ; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], L..C9(2)
; ASM32PWR4-DAG: lfd 1, 0([[REGD]]) ; ASM32PWR4-DAG: lfd 1, 0([[REGD]])
; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2) ; ASM32PWR4-DAG: lwz [[REGF:[0-9]+]], L..C8(2)
; ASM32PWR4-DAG: lfs 2, 0([[REGF]]) ; ASM32PWR4-DAG: lfs 2, 0([[REGF]])
; ASM32PWR4-DAG: stfd 1, 52(1) ; ASM32PWR4-DAG: stfd 1, 52(1)
; ASM32PWR4-DAG: stfs 2, 60(1) ; ASM32PWR4-DAG: stfs 2, 60(1)
; ASM32PWR4-DAG: stfd 1, 72(1) ; ASM32PWR4-DAG: stfd 1, 72(1)
; ASM32PWR4-DAG: lwz 10, 72(1) ; ASM32PWR4-DAG: lwz 10, 72(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float3 ; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80 ; ASM32PWR4-NEXT: addi 1, 1, 80
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; In 64-bit the double arg is not written to memory because it is fully stored in the last 64-bit GPR. ; In 64-bit the double arg is not written to memory because it is fully stored in the last 64-bit GPR.
; 64BIT-DAG: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-DAG: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = LI8 1 ; 64BIT-DAG: $x3 = LI8 1
; 64BIT-DAG: $x4 = LI8 2 ; 64BIT-DAG: $x4 = LI8 2
; 64BIT-DAG: $x5 = LI8 3 ; 64BIT-DAG: $x5 = LI8 3
; 64BIT-DAG: $x6 = LI8 4 ; 64BIT-DAG: $x6 = LI8 4
; 64BIT-DAG: $x7 = LI8 5 ; 64BIT-DAG: $x7 = LI8 5
; 64BIT-DAG: $x8 = LI8 6 ; 64BIT-DAG: $x8 = LI8 6
; 64BIT-DAG: $x9 = LI8 7 ; 64BIT-DAG: $x9 = LI8 7
; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d) ; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got) ; 64BIT-DAG: renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $f2 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f) ; 64BIT-DAG: renamable $f2 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
; 64BIT-DAG: STFS renamable $f2, 112, $x1 :: (store 4) ; 64BIT-DAG: STFS renamable $f2, 112, $x1 :: (store 4)
; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0) ; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 64BIT-DAG: renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0) ; 64BIT-DAG: renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0)
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-DAG: li 3, 1 ; ASM64PWR4-DAG: li 3, 1
; ASM64PWR4-DAG: li 4, 2 ; ASM64PWR4-DAG: li 4, 2
; ASM64PWR4-DAG: li 5, 3 ; ASM64PWR4-DAG: li 5, 3
; ASM64PWR4-DAG: li 6, 4 ; ASM64PWR4-DAG: li 6, 4
; ASM64PWR4-DAG: li 7, 5 ; ASM64PWR4-DAG: li 7, 5
; ASM64PWR4-DAG: li 8, 6 ; ASM64PWR4-DAG: li 8, 6
; ASM64PWR4-DAG: li 9, 7 ; ASM64PWR4-DAG: li 9, 7
; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2) ; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], L..C8(2)
; ASM64PWR4-DAG: lfd 1, 0([[REGD]]) ; ASM64PWR4-DAG: lfd 1, 0([[REGD]])
; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2) ; ASM64PWR4-DAG: ld [[REGF:[0-9]+]], L..C7(2)
; ASM64PWR4-DAG: lfs 2, 0([[REGF]]) ; ASM64PWR4-DAG: lfs 2, 0([[REGF]])
; ASM64PWR4-DAG: stfs 2, 112(1) ; ASM64PWR4-DAG: stfs 2, 112(1)
; ASM64PWR4-DAG: stfd 1, 120(1) ; ASM64PWR4-DAG: stfd 1, 120(1)
; ASM64PWR4-DAG: ld 10, 120(1) ; ASM64PWR4-DAG: ld 10, 120(1)
; ASM64PWR4-NEXT: bl .test_stackarg_float3 ; ASM64PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128 ; ASM64PWR4-NEXT: addi 1, 1, 128
define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) { define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) {
entry: entry:
%add = add nsw i32 %i1, %i2 %add = add nsw i32 %i1, %i2
%add1 = add nsw i32 %add, %i3 %add1 = add nsw i32 %add, %i3
%add2 = add nsw i32 %add1, %i4 %add2 = add nsw i32 %add1, %i4
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