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Differential D78352 Diff 258341 mlir/lib/Dialect/StandardOps/IR/Ops.cpp

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mlir/lib/Dialect/StandardOps/IR/Ops.cpp

Show First 20 Lines • Show All 475 Lines • ▼ Show 20 Lines case AtomicRMWKind::muli:
break; break;
default: default:
break; break;
} }
return success(); return success();
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GenericAtomicRMWOp
//===----------------------------------------------------------------------===//
void GenericAtomicRMWOp::build(Builder *builder, OperationState &result,
Value memref, ValueRange ivs) {
result.addOperands(memref);
result.addOperands(ivs);
if (auto memrefType = memref.getType().dyn_cast<MemRefType>()) {
Type elementType = memrefType.getElementType();
result.addTypes(elementType);
Region *bodyRegion = result.addRegion();
bodyRegion->push_back(new Block());
bodyRegion->front().addArgument(elementType);
}
}
static LogicalResult verify(GenericAtomicRMWOp op) {
auto &block = op.body().front();
if (block.getNumArguments() != 1)
return op.emitOpError("expected single number of entry block arguments");
if (op.getResult().getType() != block.getArgument(0).getType())
return op.emitOpError(
"expected block argument of the same type result type");
return success();
}
flaubUnsubmitted
Done
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Could we add a check that all the ops in the region are side-effect free?

flaub: Could we add a check that all the ops in the region are side-effect free?
pifon2aAuthorUnsubmitted
Done
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done! https://reviews.llvm.org/D78559

pifon2a: done! https://reviews.llvm.org/D78559
static ParseResult parseGenericAtomicRMWOp(OpAsmParser &parser,
OperationState &result) {
OpAsmParser::OperandType memref;
Type memrefType;
SmallVector<OpAsmParser::OperandType, 4> ivs;
Type indexType = parser.getBuilder().getIndexType();
if (parser.parseOperand(memref) ||
parser.parseOperandList(ivs, OpAsmParser::Delimiter::Square) ||
parser.parseColonType(memrefType) ||
parser.resolveOperand(memref, memrefType, result.operands) ||
parser.resolveOperands(ivs, indexType, result.operands))
return failure();
Region *body = result.addRegion();
if (parser.parseRegion(*body, llvm::None, llvm::None))
return failure();
result.types.push_back(memrefType.cast<MemRefType>().getElementType());
return success();
}
static void print(OpAsmPrinter &p, GenericAtomicRMWOp op) {
p << op.getOperationName() << ' ' << op.memref() << " [" << op.indices()
<< "] : " << op.memref().getType();
p.printRegion(op.body());
p.printOptionalAttrDict(op.getAttrs());
}
//===----------------------------------------------------------------------===//
// AtomicYieldOp
//===----------------------------------------------------------------------===//
static LogicalResult verify(AtomicYieldOp op) {
Type parentType = op.getParentOp()->getResultTypes().front();
Type resultType = op.result().getType();
if (parentType != resultType)
return op.emitOpError() << "types mismatch between yield op: " << resultType
<< " and its parent: " << parentType;
return success();
}
//===----------------------------------------------------------------------===//
// BranchOp // BranchOp
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
namespace { namespace {
/// Simplify a branch to a block that has a single predecessor. This effectively /// Simplify a branch to a block that has a single predecessor. This effectively
/// merges the two blocks. /// merges the two blocks.
struct SimplifyBrToBlockWithSinglePred : public OpRewritePattern<BranchOp> { struct SimplifyBrToBlockWithSinglePred : public OpRewritePattern<BranchOp> {
using OpRewritePattern<BranchOp>::OpRewritePattern; using OpRewritePattern<BranchOp>::OpRewritePattern;
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