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llvm/lib/Target/RISCV/RISCV.td
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| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // RISC-V subtarget features and instruction predicates. | // RISC-V subtarget features and instruction predicates. | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| def FeatureStdExtM | def FeatureStdExtM | ||||
| : SubtargetFeature<"m", "HasStdExtM", "true", | : SubtargetFeature<"m", "HasStdExtM", "true", | ||||
| "'M' (Integer Multiplication and Division)">; | "'M' (Integer Multiplication and Division)">; | ||||
| def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, | def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, | ||||
| AssemblerPredicate<"FeatureStdExtM", | AssemblerPredicate<(all_of FeatureStdExtM), | ||||
| "'M' (Integer Multiplication and Division)">; | "'M' (Integer Multiplication and Division)">; | ||||
| def FeatureStdExtA | def FeatureStdExtA | ||||
| : SubtargetFeature<"a", "HasStdExtA", "true", | : SubtargetFeature<"a", "HasStdExtA", "true", | ||||
| "'A' (Atomic Instructions)">; | "'A' (Atomic Instructions)">; | ||||
| def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, | def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, | ||||
| AssemblerPredicate<"FeatureStdExtA", | AssemblerPredicate<(all_of FeatureStdExtA), | ||||
| "'A' (Atomic Instructions)">; | "'A' (Atomic Instructions)">; | ||||
| def FeatureStdExtF | def FeatureStdExtF | ||||
| : SubtargetFeature<"f", "HasStdExtF", "true", | : SubtargetFeature<"f", "HasStdExtF", "true", | ||||
| "'F' (Single-Precision Floating-Point)">; | "'F' (Single-Precision Floating-Point)">; | ||||
| def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, | def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, | ||||
| AssemblerPredicate<"FeatureStdExtF", | AssemblerPredicate<(all_of FeatureStdExtF), | ||||
| "'F' (Single-Precision Floating-Point)">; | "'F' (Single-Precision Floating-Point)">; | ||||
| def FeatureStdExtD | def FeatureStdExtD | ||||
| : SubtargetFeature<"d", "HasStdExtD", "true", | : SubtargetFeature<"d", "HasStdExtD", "true", | ||||
| "'D' (Double-Precision Floating-Point)", | "'D' (Double-Precision Floating-Point)", | ||||
| [FeatureStdExtF]>; | [FeatureStdExtF]>; | ||||
| def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, | def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, | ||||
| AssemblerPredicate<"FeatureStdExtD", | AssemblerPredicate<(all_of FeatureStdExtD), | ||||
| "'D' (Double-Precision Floating-Point)">; | "'D' (Double-Precision Floating-Point)">; | ||||
| def FeatureStdExtC | def FeatureStdExtC | ||||
| : SubtargetFeature<"c", "HasStdExtC", "true", | : SubtargetFeature<"c", "HasStdExtC", "true", | ||||
| "'C' (Compressed Instructions)">; | "'C' (Compressed Instructions)">; | ||||
| def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, | def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, | ||||
| AssemblerPredicate<"FeatureStdExtC", | AssemblerPredicate<(all_of FeatureStdExtC), | ||||
| "'C' (Compressed Instructions)">; | "'C' (Compressed Instructions)">; | ||||
| def FeatureRVCHints | def FeatureRVCHints | ||||
| : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", | : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", | ||||
| "Enable RVC Hint Instructions.">; | "Enable RVC Hint Instructions.">; | ||||
| def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, | def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, | ||||
| AssemblerPredicate<"FeatureRVCHints", | AssemblerPredicate<(all_of FeatureRVCHints), | ||||
| "RVC Hint Instructions">; | "RVC Hint Instructions">; | ||||
| def Feature64Bit | def Feature64Bit | ||||
| : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; | : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; | ||||
| def IsRV64 : Predicate<"Subtarget->is64Bit()">, | def IsRV64 : Predicate<"Subtarget->is64Bit()">, | ||||
| AssemblerPredicate<"Feature64Bit", | AssemblerPredicate<(all_of Feature64Bit), | ||||
| "RV64I Base Instruction Set">; | "RV64I Base Instruction Set">; | ||||
| def IsRV32 : Predicate<"!Subtarget->is64Bit()">, | def IsRV32 : Predicate<"!Subtarget->is64Bit()">, | ||||
| AssemblerPredicate<"!Feature64Bit", | AssemblerPredicate<(all_of (not Feature64Bit)), | ||||
| "RV32I Base Instruction Set">; | "RV32I Base Instruction Set">; | ||||
| def RV64 : HwMode<"+64bit">; | def RV64 : HwMode<"+64bit">; | ||||
| def RV32 : HwMode<"-64bit">; | def RV32 : HwMode<"-64bit">; | ||||
| def FeatureRV32E | def FeatureRV32E | ||||
| : SubtargetFeature<"e", "IsRV32E", "true", | : SubtargetFeature<"e", "IsRV32E", "true", | ||||
| "Implements RV32E (provides 16 rather than 32 GPRs)">; | "Implements RV32E (provides 16 rather than 32 GPRs)">; | ||||
| def IsRV32E : Predicate<"Subtarget->isRV32E()">, | def IsRV32E : Predicate<"Subtarget->isRV32E()">, | ||||
| AssemblerPredicate<"FeatureRV32E">; | AssemblerPredicate<(all_of FeatureRV32E)>; | ||||
| def FeatureRelax | def FeatureRelax | ||||
| : SubtargetFeature<"relax", "EnableLinkerRelax", "true", | : SubtargetFeature<"relax", "EnableLinkerRelax", "true", | ||||
| "Enable Linker relaxation.">; | "Enable Linker relaxation.">; | ||||
| foreach i = {1-31} in | foreach i = {1-31} in | ||||
| def FeatureReserveX#i : | def FeatureReserveX#i : | ||||
| SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", | SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", | ||||
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