Differential D73711 Diff 245980 llvm/lib/Target/AArch64/AArch64InstrInfo.h

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llvm/lib/Target/AArch64/AArch64InstrInfo.h

Show First 20 Lines • Show All 265 Lines • ▼ Show 20 Lines	bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
unsigned &Flags) const override;		unsigned &Flags) const override;
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,		void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
const outliner::OutlinedFunction &OF) const override;		const outliner::OutlinedFunction &OF) const override;
MachineBasicBlock::iterator		MachineBasicBlock::iterator
insertOutlinedCall(Module &M, MachineBasicBlock &MBB,		insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &It, MachineFunction &MF,		MachineBasicBlock::iterator &It, MachineFunction &MF,
const outliner::Candidate &C) const override;		const outliner::Candidate &C) const override;
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;		bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
		/// Returns the vector element size (B, H, S or D) of an SVE opcode.
		uint64_t getElementSizeForOpcode(unsigned Opc) const;
/// Returns true if the instruction has a shift by immediate that can be		/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.		/// executed in one cycle less.
static bool isFalkorShiftExtFast(const MachineInstr &MI);		static bool isFalkorShiftExtFast(const MachineInstr &MI);
/// Return true if the instructions is a SEH instruciton used for unwinding		/// Return true if the instructions is a SEH instruciton used for unwinding
/// on Windows.		/// on Windows.
static bool isSEHInstruction(const MachineInstr &MI);		static bool isSEHInstruction(const MachineInstr &MI);

Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,		Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
Register Reg) const override;		Register Reg) const override;

Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,		Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
Register Reg) const override;		Register Reg) const override;

#define GET_INSTRINFO_HELPER_DECLS		#define GET_INSTRINFO_HELPER_DECLS
#include "AArch64GenInstrInfo.inc"		#include "AArch64GenInstrInfo.inc"

protected:		protected:
/// If the specific machine instruction is an instruction that moves/copies		/// If the specific machine instruction is an instruction that moves/copies
/// value from one register to another register return destination and source		/// value from one register to another register return destination and source
/// registers as machine operands.		/// registers as machine operands.
Optional<DestSourcePair>		Optional<DestSourcePair>
isCopyInstrImpl(const MachineInstr &MI) const override;		isCopyInstrImpl(const MachineInstr &MI) const override;

private:		private:
		unsigned getInstBundleLength(const MachineInstr &MI) const;

/// Sets the offsets on outlined instructions in \p MBB which use SP		/// Sets the offsets on outlined instructions in \p MBB which use SP
/// so that they will be valid post-outlining.		/// so that they will be valid post-outlining.
///		///
/// \param MBB A \p MachineBasicBlock in an outlined function.		/// \param MBB A \p MachineBasicBlock in an outlined function.
void fixupPostOutline(MachineBasicBlock &MBB) const;		void fixupPostOutline(MachineBasicBlock &MBB) const;

void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,		void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
MachineBasicBlock *TBB,		MachineBasicBlock *TBB,
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
}		}

static inline bool isIndirectBranchOpcode(int Opc) {		static inline bool isIndirectBranchOpcode(int Opc) {
return Opc == AArch64::BR;		return Opc == AArch64::BR;
}		}

// struct TSFlags {		// struct TSFlags {
#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits		#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit		#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit
		#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
// }		// }

namespace AArch64 {		namespace AArch64 {

enum ElementSizeType {		enum ElementSizeType {
ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),		ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),
ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),		ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),
ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1),		ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1),
ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2),		ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2),
ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3),		ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3),
ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4),		ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4),
};		};

enum DestructiveInstType {		enum DestructiveInstType {
DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),		DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf),
NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),		NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),		DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
		DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2),
		DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3),
		DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4),
		DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5),
		DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6),
		DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7),
		DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8),
		};

		enum FalseLaneType {
		FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3),
		FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1),
		FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2),
};		};

#undef TSFLAG_ELEMENT_SIZE_TYPE		#undef TSFLAG_ELEMENT_SIZE_TYPE
#undef TSFLAG_DESTRUCTIVE_INST_TYPE		#undef TSFLAG_DESTRUCTIVE_INST_TYPE
		#undef TSFLAG_FALSE_LANE_TYPE

		int getSVEPseudoMap(uint16_t Opcode);
		int getSVERevInstr(uint16_t Opcode);
		int getSVEOrigInstr(uint16_t Opcode);
}		}

} // end namespace llvm		} // end namespace llvm

#endif		#endif