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llvm/test/CodeGen/AMDGPU/omod.ll
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s | ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s | ||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s | ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s | ||||
; IEEE bit enabled for compute kernel, no shouldn't use. | ; IEEE bit enabled for compute kernel, no shouldn't use. | ||||
; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_signed_zeros: | ; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_signed_zeros: | ||||
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] | ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] | ||||
; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} | ; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}} | ||||
; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}} | ; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}} | ||||
define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(float addrspace(1)* %out, float addrspace(1)* %aptr) #4 { | define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(float addrspace(1)* %out, float addrspace(1)* %aptr) #4 { | ||||
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