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llvm/test/CodeGen/AMDGPU/madmk.ll
| ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s | ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s | ||||
| ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s | ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s | ||||
| ; FIXME: None of these trigger madmk emission anymore. It is still | ; FIXME: None of these trigger madmk emission anymore. It is still | ||||
| ; possible, but requires the correct registers to be used which is | ; possible, but requires the correct registers to be used which is | ||||
| ; hard to trigger. | ; hard to trigger. | ||||
| declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone | declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone | ||||
| declare float @llvm.fabs.f32(float) nounwind readnone | declare float @llvm.fabs.f32(float) nounwind readnone | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | define amdgpu_kernel void @s_s_madmk_f32(float addrspace(1)* noalias %out, [8 x i32], float %a, [8 x i32], float %b) nounwind { | ||||
| %mul = fmul float %a, 10.0 | %mul = fmul float %a, 10.0 | ||||
| %madmk = fadd float %mul, %b | %madmk = fadd float %mul, %b | ||||
| store float %madmk, float addrspace(1)* %out.gep, align 4 | store float %madmk, float addrspace(1)* %out.gep, align 4 | ||||
| ret void | ret void | ||||
| } | } | ||||
| ; GCN-LABEL: {{^}}v_s_madmk_f32: | ; GCN-LABEL: {{^}}v_s_madmk_f32: | ||||
| ; GCN: s_load_dword [[SREG:s[0-9]+]] | ; GCN-DAG: s_load_dword [[SREG:s[0-9]+]] | ||||
| ; GCN: buffer_load_dword [[VREG1:v[0-9]+]] | ; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]] | ||||
| ; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] | ; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] | ||||
| ; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] | ; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] | ||||
| ; GCN: s_endpgm | ; GCN: s_endpgm | ||||
| define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind { | define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind { | ||||
| %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone | %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone | ||||
| %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid | %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid | ||||
| %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid | %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid | ||||
| %a = load float, float addrspace(1)* %gep.0, align 4 | %a = load float, float addrspace(1)* %gep.0, align 4 | ||||
| ▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines | |||||