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Differential D74594 Diff 244599 llvm/test/CodeGen/AMDGPU/madmk.ll

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llvm/test/CodeGen/AMDGPU/madmk.ll

1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 1​; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 2​; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3 3​
4 ; FIXME: None of these trigger madmk emission anymore. It is still 4​ ; FIXME: None of these trigger madmk emission anymore. It is still
5 ; possible, but requires the correct registers to be used which is 5​ ; possible, but requires the correct registers to be used which is
6 ; hard to trigger. 6​ ; hard to trigger.
7 7​
8declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 8​declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
9declare float @llvm.fabs.f32(float) nounwind readnone 9​declare float @llvm.fabs.f32(float) nounwind readnone
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Line(s)86define amdgpu_kernel void @s_s_madmk_f32(float addrspace(1)* noalias %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {
89 89​
90 %mul = fmul float %a, 10.0 90​ %mul = fmul float %a, 10.0
91 %madmk = fadd float %mul, %b 91​ %madmk = fadd float %mul, %b
92 store float %madmk, float addrspace(1)* %out.gep, align 4 92​ store float %madmk, float addrspace(1)* %out.gep, align 4
93 ret void 93​ ret void
94} 94​}
95 95​
96; GCN-LABEL: {{^}}v_s_madmk_f32: 96​; GCN-LABEL: {{^}}v_s_madmk_f32:
97; GCN: s_load_dword [[SREG:s[0-9]+]] 97​; GCN-DAG: s_load_dword [[SREG:s[0-9]+]]
98; GCN: buffer_load_dword [[VREG1:v[0-9]+]] 98​; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]]
99; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] 99​; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]]
100; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] 100​; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]]
101; GCN: s_endpgm 101​; GCN: s_endpgm
102define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind { 102​define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind {
103 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 103​ %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
104 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 104​ %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
105 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 105​ %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
106 %a = load float, float addrspace(1)* %gep.0, align 4 106​ %a = load float, float addrspace(1)* %gep.0, align 4
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines