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llvm/lib/Target/X86/X86InstrInfo.td
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def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; | ||||
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; | ||||
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, | ||||
[SDNPHasChain]>; | [SDNPHasChain]>; | ||||
def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; | ||||
def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; | ||||
def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; | |||||
def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, | def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, | ||||
[SDNPHasChain, SDNPSideEffect]>; | [SDNPHasChain, SDNPSideEffect]>; | ||||
def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, | def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, | ||||
[SDNPHasChain, SDNPSideEffect]>; | [SDNPHasChain, SDNPSideEffect]>; | ||||
def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, | def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, | ||||
[SDNPHasChain, SDNPSideEffect]>; | [SDNPHasChain, SDNPSideEffect]>; | ||||
▲ Show 20 Lines • Show All 1,617 Lines • ▼ Show 20 Lines | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, | ||||
(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), | ||||
"mov{b}\t{$src, $dst|$dst, $src}", []>, | "mov{b}\t{$src, $dst|$dst, $src}", []>, | ||||
Sched<[WriteLoad]>; | Sched<[WriteLoad]>; | ||||
} | } | ||||
// Condition code ops, incl. set if equal/not equal/... | // Condition code ops, incl. set if equal/not equal/... | ||||
let SchedRW = [WriteLAHFSAHF] in { | let SchedRW = [WriteLAHFSAHF] in { | ||||
let Defs = [EFLAGS], Uses = [AH] in | let Defs = [EFLAGS], Uses = [AH], hasSideEffects = 0 in | ||||
def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, // flags = AH | ||||
[(set EFLAGS, (X86sahf AH))]>, | |||||
Requires<[HasLAHFSAHF]>; | Requires<[HasLAHFSAHF]>; | ||||
let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in | let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in | ||||
def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags | ||||
Requires<[HasLAHFSAHF]>; | Requires<[HasLAHFSAHF]>; | ||||
} // SchedRW | } // SchedRW | ||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
// Bit tests instructions: BT, BTS, BTR, BTC. | // Bit tests instructions: BT, BTS, BTR, BTC. | ||||
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