Differential D71424 Diff 234029 llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll

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# llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll

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1 | ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s | ||||
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2 | | ||||

3 | ; ADDHNB | ||||

4 | | ||||

5 | define <vscale x 16 x i8> @addhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { | ||||

6 | ; CHECK-LABEL: addhnb_h: | ||||

7 | ; CHECK: addhnb z0.b, z0.h, z1.h | ||||

8 | ; CHECK-NEXT: ret | ||||

9 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16> %a, | ||||

10 | <vscale x 8 x i16> %b) | ||||

11 | ret <vscale x 16 x i8> %out | ||||

12 | } | ||||

13 | | ||||

14 | define <vscale x 8 x i16> @addhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { | ||||

15 | ; CHECK-LABEL: addhnb_s: | ||||

16 | ; CHECK: addhnb z0.h, z0.s, z1.s | ||||

17 | ; CHECK-NEXT: ret | ||||

18 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32> %a, | ||||

19 | <vscale x 4 x i32> %b) | ||||

20 | ret <vscale x 8 x i16> %out | ||||

21 | } | ||||

22 | | ||||

23 | define <vscale x 4 x i32> @addhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { | ||||

24 | ; CHECK-LABEL: addhnb_d: | ||||

25 | ; CHECK: addhnb z0.s, z0.d, z1.d | ||||

26 | ; CHECK-NEXT: ret | ||||

27 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64> %a, | ||||

28 | <vscale x 2 x i64> %b) | ||||

29 | ret <vscale x 4 x i32> %out | ||||

30 | } | ||||

31 | | ||||

32 | ; ADDHNT | ||||

33 | | ||||

34 | define <vscale x 16 x i8> @addhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { | ||||

35 | ; CHECK-LABEL: addhnt_h: | ||||

36 | ; CHECK: addhnt z0.b, z1.h, z2.h | ||||

37 | ; CHECK-NEXT: ret | ||||

38 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8> %a, | ||||

39 | <vscale x 8 x i16> %b, | ||||

40 | <vscale x 8 x i16> %c) | ||||

41 | ret <vscale x 16 x i8> %out | ||||

42 | } | ||||

43 | | ||||

44 | define <vscale x 8 x i16> @addhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { | ||||

45 | ; CHECK-LABEL: addhnt_s: | ||||

46 | ; CHECK: addhnt z0.h, z1.s, z2.s | ||||

47 | ; CHECK-NEXT: ret | ||||

48 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16> %a, | ||||

49 | <vscale x 4 x i32> %b, | ||||

50 | <vscale x 4 x i32> %c) | ||||

51 | ret <vscale x 8 x i16> %out | ||||

52 | } | ||||

53 | | ||||

54 | define <vscale x 4 x i32> @addhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { | ||||

55 | ; CHECK-LABEL: addhnt_d: | ||||

56 | ; CHECK: addhnt z0.s, z1.d, z2.d | ||||

57 | ; CHECK-NEXT: ret | ||||

58 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32> %a, | ||||

59 | <vscale x 2 x i64> %b, | ||||

60 | <vscale x 2 x i64> %c) | ||||

61 | ret <vscale x 4 x i32> %out | ||||

62 | } | ||||

63 | | ||||

64 | ; RADDHNB | ||||

65 | | ||||

66 | define <vscale x 16 x i8> @raddhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { | ||||

67 | ; CHECK-LABEL: raddhnb_h: | ||||

68 | ; CHECK: raddhnb z0.b, z0.h, z1.h | ||||

69 | ; CHECK-NEXT: ret | ||||

70 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16> %a, | ||||

71 | <vscale x 8 x i16> %b) | ||||

72 | ret <vscale x 16 x i8> %out | ||||

73 | } | ||||

74 | | ||||

75 | define <vscale x 8 x i16> @raddhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { | ||||

76 | ; CHECK-LABEL: raddhnb_s: | ||||

77 | ; CHECK: raddhnb z0.h, z0.s, z1.s | ||||

78 | ; CHECK-NEXT: ret | ||||

79 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32> %a, | ||||

80 | <vscale x 4 x i32> %b) | ||||

81 | ret <vscale x 8 x i16> %out | ||||

82 | } | ||||

83 | | ||||

84 | define <vscale x 4 x i32> @raddhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { | ||||

85 | ; CHECK-LABEL: raddhnb_d: | ||||

86 | ; CHECK: raddhnb z0.s, z0.d, z1.d | ||||

87 | ; CHECK-NEXT: ret | ||||

88 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64> %a, | ||||

89 | <vscale x 2 x i64> %b) | ||||

90 | ret <vscale x 4 x i32> %out | ||||

91 | } | ||||

92 | | ||||

93 | ; RADDHNT | ||||

94 | | ||||

95 | define <vscale x 16 x i8> @raddhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { | ||||

96 | ; CHECK-LABEL: raddhnt_h: | ||||

97 | ; CHECK: raddhnt z0.b, z1.h, z2.h | ||||

98 | ; CHECK-NEXT: ret | ||||

99 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8> %a, | ||||

100 | <vscale x 8 x i16> %b, | ||||

101 | <vscale x 8 x i16> %c) | ||||

102 | ret <vscale x 16 x i8> %out | ||||

103 | } | ||||

104 | | ||||

105 | define <vscale x 8 x i16> @raddhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { | ||||

106 | ; CHECK-LABEL: raddhnt_s: | ||||

107 | ; CHECK: raddhnt z0.h, z1.s, z2.s | ||||

108 | ; CHECK-NEXT: ret | ||||

109 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16> %a, | ||||

110 | <vscale x 4 x i32> %b, | ||||

111 | <vscale x 4 x i32> %c) | ||||

112 | ret <vscale x 8 x i16> %out | ||||

113 | } | ||||

114 | | ||||

115 | define <vscale x 4 x i32> @raddhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { | ||||

116 | ; CHECK-LABEL: raddhnt_d: | ||||

117 | ; CHECK: raddhnt z0.s, z1.d, z2.d | ||||

118 | ; CHECK-NEXT: ret | ||||

119 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32> %a, | ||||

120 | <vscale x 2 x i64> %b, | ||||

121 | <vscale x 2 x i64> %c) | ||||

122 | ret <vscale x 4 x i32> %out | ||||

123 | } | ||||

124 | | ||||

125 | ; RSUBHNB | ||||

126 | | ||||

127 | define <vscale x 16 x i8> @rsubhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { | ||||

128 | ; CHECK-LABEL: rsubhnb_h: | ||||

129 | ; CHECK: rsubhnb z0.b, z0.h, z1.h | ||||

130 | ; CHECK-NEXT: ret | ||||

131 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16> %a, | ||||

132 | <vscale x 8 x i16> %b) | ||||

133 | ret <vscale x 16 x i8> %out | ||||

134 | } | ||||

135 | | ||||

136 | define <vscale x 8 x i16> @rsubhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { | ||||

137 | ; CHECK-LABEL: rsubhnb_s: | ||||

138 | ; CHECK: rsubhnb z0.h, z0.s, z1.s | ||||

139 | ; CHECK-NEXT: ret | ||||

140 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32> %a, | ||||

141 | <vscale x 4 x i32> %b) | ||||

142 | ret <vscale x 8 x i16> %out | ||||

143 | } | ||||

144 | | ||||

145 | define <vscale x 4 x i32> @rsubhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { | ||||

146 | ; CHECK-LABEL: rsubhnb_d: | ||||

147 | ; CHECK: rsubhnb z0.s, z0.d, z1.d | ||||

148 | ; CHECK-NEXT: ret | ||||

149 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64> %a, | ||||

150 | <vscale x 2 x i64> %b) | ||||

151 | ret <vscale x 4 x i32> %out | ||||

152 | } | ||||

153 | | ||||

154 | ; RSUBHNT | ||||

155 | | ||||

156 | define <vscale x 16 x i8> @rsubhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { | ||||

157 | ; CHECK-LABEL: rsubhnt_h: | ||||

158 | ; CHECK: rsubhnt z0.b, z1.h, z2.h | ||||

159 | ; CHECK-NEXT: ret | ||||

160 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8> %a, | ||||

161 | <vscale x 8 x i16> %b, | ||||

162 | <vscale x 8 x i16> %c) | ||||

163 | ret <vscale x 16 x i8> %out | ||||

164 | } | ||||

165 | | ||||

166 | define <vscale x 8 x i16> @rsubhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { | ||||

167 | ; CHECK-LABEL: rsubhnt_s: | ||||

168 | ; CHECK: rsubhnt z0.h, z1.s, z2.s | ||||

169 | ; CHECK-NEXT: ret | ||||

170 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16> %a, | ||||

171 | <vscale x 4 x i32> %b, | ||||

172 | <vscale x 4 x i32> %c) | ||||

173 | ret <vscale x 8 x i16> %out | ||||

174 | } | ||||

175 | | ||||

176 | define <vscale x 4 x i32> @rsubhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { | ||||

177 | ; CHECK-LABEL: rsubhnt_d: | ||||

178 | ; CHECK: rsubhnt z0.s, z1.d, z2.d | ||||

179 | ; CHECK-NEXT: ret | ||||

180 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32> %a, | ||||

181 | <vscale x 2 x i64> %b, | ||||

182 | <vscale x 2 x i64> %c) | ||||

183 | ret <vscale x 4 x i32> %out | ||||

184 | } | ||||

185 | | ||||

186 | ; SUBHNB | ||||

187 | | ||||

188 | define <vscale x 16 x i8> @subhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { | ||||

189 | ; CHECK-LABEL: subhnb_h: | ||||

190 | ; CHECK: subhnb z0.b, z0.h, z1.h | ||||

191 | ; CHECK-NEXT: ret | ||||

192 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16> %a, | ||||

193 | <vscale x 8 x i16> %b) | ||||

194 | ret <vscale x 16 x i8> %out | ||||

195 | } | ||||

196 | | ||||

197 | define <vscale x 8 x i16> @subhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { | ||||

198 | ; CHECK-LABEL: subhnb_s: | ||||

199 | ; CHECK: subhnb z0.h, z0.s, z1.s | ||||

200 | ; CHECK-NEXT: ret | ||||

201 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32> %a, | ||||

202 | <vscale x 4 x i32> %b) | ||||

203 | ret <vscale x 8 x i16> %out | ||||

204 | } | ||||

205 | | ||||

206 | define <vscale x 4 x i32> @subhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { | ||||

207 | ; CHECK-LABEL: subhnb_d: | ||||

208 | ; CHECK: subhnb z0.s, z0.d, z1.d | ||||

209 | ; CHECK-NEXT: ret | ||||

210 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64> %a, | ||||

211 | <vscale x 2 x i64> %b) | ||||

212 | ret <vscale x 4 x i32> %out | ||||

213 | } | ||||

214 | | ||||

215 | ; SUBHNT | ||||

216 | | ||||

217 | define <vscale x 16 x i8> @subhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { | ||||

218 | ; CHECK-LABEL: subhnt_h: | ||||

219 | ; CHECK: subhnt z0.b, z1.h, z2.h | ||||

220 | ; CHECK-NEXT: ret | ||||

221 | %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8> %a, | ||||

222 | <vscale x 8 x i16> %b, | ||||

223 | <vscale x 8 x i16> %c) | ||||

224 | ret <vscale x 16 x i8> %out | ||||

225 | } | ||||

226 | | ||||

227 | define <vscale x 8 x i16> @subhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { | ||||

228 | ; CHECK-LABEL: subhnt_s: | ||||

229 | ; CHECK: subhnt z0.h, z1.s, z2.s | ||||

230 | ; CHECK-NEXT: ret | ||||

231 | %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16> %a, | ||||

232 | <vscale x 4 x i32> %b, | ||||

233 | <vscale x 4 x i32> %c) | ||||

234 | ret <vscale x 8 x i16> %out | ||||

235 | } | ||||

236 | | ||||

237 | define <vscale x 4 x i32> @subhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { | ||||

238 | ; CHECK-LABEL: subhnt_d: | ||||

239 | ; CHECK: subhnt z0.s, z1.d, z2.d | ||||

240 | ; CHECK-NEXT: ret | ||||

241 | %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32> %a, | ||||

242 | <vscale x 2 x i64> %b, | ||||

243 | <vscale x 2 x i64> %c) | ||||

244 | ret <vscale x 4 x i32> %out | ||||

245 | } | ||||

246 | | ||||

247 | | ||||

248 | declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

249 | declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

250 | declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

251 | | ||||

252 | declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

253 | declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

254 | declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

255 | | ||||

256 | declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

257 | declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

258 | declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

259 | | ||||

260 | declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

261 | declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

262 | declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

263 | | ||||

264 | declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

265 | declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

266 | declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

267 | | ||||

268 | declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

269 | declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

270 | declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

271 | | ||||

272 | declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

273 | declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

274 | declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) | ||||

275 | | ||||

276 | declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>) | ||||

277 | declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>) | ||||

278 | declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>) |