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Differential D69723 Diff 229352 llvm/test/CodeGen/RISCV/vararg.ll

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llvm/test/CodeGen/RISCV/vararg.ll

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; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1: ; ILP32-ILP32F-WITHFP-LABEL: va1:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 48 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 0
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 16
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 80
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 4 ; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 4
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 0
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%argp.cur = load i8*, i8** %va, align 4 %argp.cur = load i8*, i8** %va, align 4
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
store i8* %argp.next, i8** %va, align 4 store i8* %argp.next, i8** %va, align 4
%2 = bitcast i8* %argp.cur to i32* %2 = bitcast i8* %argp.cur to i32*
▲ Show 20 Lines • Show All 1,643 Lines • ▼ Show 20 Lines
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414 ; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 280 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 280
; ILP32-ILP32F-FPELIM-NEXT: add a1, sp, a1 ; ILP32-ILP32F-FPELIM-NEXT: add a1, sp, a1
; ILP32-ILP32F-FPELIM-NEXT: mv a1, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv a1, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414 ; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304
; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1 ; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1
; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va_large_stack: ; ILP32-ILP32F-WITHFP-LABEL: va_large_stack:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -2032 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -2032
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 1996(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 1996(sp)
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 1992(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 1992(sp)
Show All 16 Lines
; ILP32-ILP32F-WITHFP-NEXT: lui a2, 1024162 ; ILP32-ILP32F-WITHFP-NEXT: lui a2, 1024162
; ILP32-ILP32F-WITHFP-NEXT: addi a2, a2, -272 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, a2, -272
; ILP32-ILP32F-WITHFP-NEXT: add a2, s0, a2 ; ILP32-ILP32F-WITHFP-NEXT: add a2, s0, a2
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 0(a2) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 0(a2)
; ILP32-ILP32F-WITHFP-NEXT: lui a1, 24414 ; ILP32-ILP32F-WITHFP-NEXT: lui a1, 24414
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728
; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1 ; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp)
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 2000
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp)
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 24414 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 304 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 304
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub sp, sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub sp, sp, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 100000048 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 100000048
Show All 29 Lines
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 280 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 280
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, sp, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, sp, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a1, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a1, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 304 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 304
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add sp, sp, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add sp, sp, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack: ; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 336 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 336
; LP64-LP64F-LP64D-FPELIM-NEXT: sub sp, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: sub sp, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 100000080 ; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 100000080
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; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 280 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 280
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336
; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack: ; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -2032
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 1960(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 1960(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 1952(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 1952(sp)
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; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -288 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -288
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, s0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, s0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(a1) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(a1)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680
; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 1968
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%large = alloca [ 100000000 x i8 ] %large = alloca [ 100000000 x i8 ]
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%argp.cur = load i8*, i8** %va, align 4 %argp.cur = load i8*, i8** %va, align 4
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
store i8* %argp.next, i8** %va, align 4 store i8* %argp.next, i8** %va, align 4
%2 = bitcast i8* %argp.cur to i32* %2 = bitcast i8* %argp.cur to i32*
%3 = load i32, i32* %2, align 4 %3 = load i32, i32* %2, align 4
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %3 ret i32 %3
} }