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Differential D69723 Diff 229352 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

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llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines	if (RI->needsStackRealignment(MF)) {
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)		BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
.addReg(VR)		.addReg(VR)
.addImm(ShiftAmount);		.addImm(ShiftAmount);
}		}
}		}
}		}
}		}

// FIXME Fix emission of .cfi_restore and .cfi_def_cfa CFI directives that can
// incorrectly affect subsequent basic blocks.
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,		void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {		MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();		MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
const RISCVRegisterInfo *RI = STI.getRegisterInfo();		const RISCVRegisterInfo *RI = STI.getRegisterInfo();
MachineFrameInfo &MFI = MF.getFrameInfo();		MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();		auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
DebugLoc DL = MBBI->getDebugLoc();		DebugLoc DL = MBBI->getDebugLoc();
const RISCVInstrInfo *TII = STI.getInstrInfo();
Register FPReg = getFPReg(STI);		Register FPReg = getFPReg(STI);
Register SPReg = getSPReg(STI);		Register SPReg = getSPReg(STI);

// Skip to before the restores of callee-saved registers		// Skip to before the restores of callee-saved registers
// FIXME: assumes exactly one instruction is used to restore each		// FIXME: assumes exactly one instruction is used to restore each
// callee-saved register.		// callee-saved register.
auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size());		auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size());

Show All 11 Lines	void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,

uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);		uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
if (FirstSPAdjustAmount) {		if (FirstSPAdjustAmount) {
uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;		uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
assert(SecondSPAdjustAmount > 0 &&		assert(SecondSPAdjustAmount > 0 &&
"SecondSPAdjustAmount should be greater than zero");		"SecondSPAdjustAmount should be greater than zero");

adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,		adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
MachineInstr::FrameDestroy);		MachineInstr::FrameDestroy);

// Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
if (!hasFP(MF)) {
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaOffset(nullptr, -FirstSPAdjustAmount));
BuildMI(MBB, LastFrameDestroy, DL,
TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
}

if (hasFP(MF)) {
// To find the instruction restoring FP from stack.
for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
if (I->mayLoad() && I->getOperand(0).isReg()) {
Register DestReg = I->getOperand(0).getReg();
if (DestReg == FPReg) {
// If there is frame pointer, after restoring $fp registers, we
// need adjust CFA back to the correct sp-based offset.
// Emit ".cfi_def_cfa $sp, CFAOffset"
uint64_t CFAOffset =
FirstSPAdjustAmount
? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
: -FPOffset;
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
BuildMI(MBB, std::next(I), DL,
TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
break;
}
}
}
}

// Add CFI directives for callee-saved registers.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
// Iterate over list of callee-saved registers and emit .cfi_restore
// directives.
for (const auto &Entry : CSI) {
Register Reg = Entry.getReg();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
nullptr, RI->getDwarfRegNum(Reg, true)));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}		}
		shiva0217Unsubmitted Done Reply Inline Actions Should we remove this cfi directive, too? shiva0217: Should we remove this cfi directive, too?
		luismarquesAuthorUnsubmitted Done Reply Inline Actions Yup, that was a silly oversight. Thanks! luismarques: Yup, that was a silly oversight. Thanks!

if (FirstSPAdjustAmount)		if (FirstSPAdjustAmount)
StackSize = FirstSPAdjustAmount;		StackSize = FirstSPAdjustAmount;

// Deallocate stack		// Deallocate stack
adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);		adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);

// After restoring $sp, we need to adjust CFA to $(sp + 0)
// Emit ".cfi_def_cfa_offset 0"
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}		}

int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,		int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
int FI,		int FI,
unsigned &FrameReg) const {		unsigned &FrameReg) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();		const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();		const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();		const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
▲ Show 20 Lines • Show All 173 Lines • Show Last 20 Lines