Differential D68673 Diff 225058 llvm/lib/Target/AMDGPU/SIInstrInfo.h

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llvm/lib/Target/AMDGPU/SIInstrInfo.h

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void loadRegFromStackSlot(MachineBasicBlock &MBB,		void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, unsigned DestReg,		MachineBasicBlock::iterator MI, unsigned DestReg,
int FrameIndex, const TargetRegisterClass *RC,		int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;		const TargetRegisterInfo *TRI) const override;

bool expandPostRAPseudo(MachineInstr &MI) const override;		bool expandPostRAPseudo(MachineInstr &MI) const override;

		// Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
		vpykhtinUnsubmitted Done Reply Inline Actions please add short desc vpykhtin: please add short desc
		// instructions. Returns a pair of generated instructions.
		// Can split either post-RA with physical registers or pre-RA with
		// virtual registers. In latter case IR needs to be in SSA form and
		// and a REG_SEQUENCE is produced to define original register.
		std::pair<MachineInstr, MachineInstr>
		expandMovDPP64(MachineInstr &MI) const;

// Returns an opcode that can be used to move a value to a \p DstRC		// Returns an opcode that can be used to move a value to a \p DstRC
// register. If there is no hardware instruction that can store to \p		// register. If there is no hardware instruction that can store to \p
// DstRC, then AMDGPU::COPY is returned.		// DstRC, then AMDGPU::COPY is returned.
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;		unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;

LLVM_READONLY		LLVM_READONLY
int commuteOpcode(unsigned Opc) const;		int commuteOpcode(unsigned Opc) const;

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