Differential D68673 Diff 225058 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 1,448 Lines • ▼ Show 20 Lines	if (SrcOp.isImm()) {
.addReg(Dst, RegState::Implicit \| RegState::Define);		.addReg(Dst, RegState::Implicit \| RegState::Define);
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)		BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
.addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))		.addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
.addReg(Dst, RegState::Implicit \| RegState::Define);		.addReg(Dst, RegState::Implicit \| RegState::Define);
}		}
MI.eraseFromParent();		MI.eraseFromParent();
break;		break;
}		}
		case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
		expandMovDPP64(MI);
		break;
		}
case AMDGPU::V_SET_INACTIVE_B32: {		case AMDGPU::V_SET_INACTIVE_B32: {
unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;		unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;		unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
BuildMI(MBB, MI, DL, get(NotOpc), Exec)		BuildMI(MBB, MI, DL, get(NotOpc), Exec)
.addReg(Exec);		.addReg(Exec);
BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())		BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
.add(MI.getOperand(2));		.add(MI.getOperand(2));
BuildMI(MBB, MI, DL, get(NotOpc), Exec)		BuildMI(MBB, MI, DL, get(NotOpc), Exec)
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines	case TargetOpcode::BUNDLE: {

MI.eraseFromParent();		MI.eraseFromParent();
break;		break;
}		}
}		}
return true;		return true;
}		}

		std::pair<MachineInstr, MachineInstr>
		SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {
		assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);

		MachineBasicBlock &MBB = *MI.getParent();
		DebugLoc DL = MBB.findDebugLoc(MI);
		MachineFunction *MF = MBB.getParent();
		MachineRegisterInfo &MRI = MF->getRegInfo();
		Register Dst = MI.getOperand(0).getReg();
		unsigned Part = 0;
		MachineInstr *Split[2];


		for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
		auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
		if (Dst.isPhysical()) {
		MovDPP.addDef(RI.getSubReg(Dst, Sub));
		} else {
		assert(MRI.isSSA());
		auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
		MovDPP.addDef(Tmp);
		}

		for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
		const MachineOperand &SrcOp = MI.getOperand(I);
		assert(!SrcOp.isFPImm());
		if (SrcOp.isImm()) {
		APInt Imm(64, SrcOp.getImm());
		Imm.ashrInPlace(Part * 32);
		MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
		} else {
		assert(SrcOp.isReg());
		Register Src = SrcOp.getReg();
		if (Src.isPhysical())
		MovDPP.addReg(RI.getSubReg(Src, Sub));
		else
		MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
		}
		}

		for (unsigned I = 3; I < MI.getNumExplicitOperands(); ++I)
		MovDPP.addImm(MI.getOperand(I).getImm());

		Split[Part] = MovDPP;
		++Part;
		}

		if (Dst.isVirtual())
		BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
		.addReg(Split[0]->getOperand(0).getReg())
		.addImm(AMDGPU::sub0)
		.addReg(Split[1]->getOperand(0).getReg())
		.addImm(AMDGPU::sub1);

		MI.eraseFromParent();
		return std::make_pair(Split[0], Split[1]);
		}

bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,		bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,
MachineOperand &Src0,		MachineOperand &Src0,
unsigned Src0OpName,		unsigned Src0OpName,
MachineOperand &Src1,		MachineOperand &Src1,
unsigned Src1OpName) const {		unsigned Src1OpName) const {
MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);		MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
if (!Src0Mods)		if (!Src0Mods)
return false;		return false;
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