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llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Show All 17 Lines | |||||
#include "llvm/Analysis/TargetTransformInfo.h" | #include "llvm/Analysis/TargetTransformInfo.h" | ||||
#include "llvm/IR/CallSite.h" | #include "llvm/IR/CallSite.h" | ||||
#include "llvm/IR/DataLayout.h" | #include "llvm/IR/DataLayout.h" | ||||
#include "llvm/IR/Function.h" | #include "llvm/IR/Function.h" | ||||
#include "llvm/IR/GetElementPtrTypeIterator.h" | #include "llvm/IR/GetElementPtrTypeIterator.h" | ||||
#include "llvm/IR/Operator.h" | #include "llvm/IR/Operator.h" | ||||
#include "llvm/IR/Type.h" | #include "llvm/IR/Type.h" | ||||
#include "llvm/Analysis/VectorUtils.h" | #include "llvm/Analysis/VectorUtils.h" | ||||
#include "llvm/CodeGen/MachineBasicBlock.h" | |||||
#include "llvm/CodeGen/MachineInstrBuilder.h" | |||||
#include "llvm/Target/TargetInstrInfo.h" | |||||
#include "llvm/Target/TargetSubtargetInfo.h" | |||||
namespace llvm { | namespace llvm { | ||||
/// \brief Base class for use as a mix-in that aids implementing | /// \brief Base class for use as a mix-in that aids implementing | ||||
/// a TargetTransformInfo-compatible class. | /// a TargetTransformInfo-compatible class. | ||||
class TargetTransformInfoImplBase { | class TargetTransformInfoImplBase { | ||||
protected: | protected: | ||||
typedef TargetTransformInfo TTI; | typedef TargetTransformInfo TTI; | ||||
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines | if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" || | ||||
Name == "llabs") | Name == "llabs") | ||||
return false; | return false; | ||||
return true; | return true; | ||||
} | } | ||||
void getUnrollingPreferences(Loop *, TTI::UnrollingPreferences &) {} | void getUnrollingPreferences(Loop *, TTI::UnrollingPreferences &) {} | ||||
void emitPatchableOp(StringRef, MachineBasicBlock &MBB, | |||||
MachineBasicBlock::iterator &MBBI) const { | |||||
auto *TII = MBB.getParent()->getSubtarget().getInstrInfo(); | |||||
auto MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), | |||||
TII->get(TargetOpcode::PATCHABLE_OP)) | |||||
.addImm(2) | |||||
.addImm(MBBI->getOpcode()); | |||||
for (auto &MO : MBBI->operands()) | |||||
MIB.addOperand(MO); | |||||
MBBI->eraseFromParent(); | |||||
} | |||||
bool isLegalAddImmediate(int64_t Imm) { return false; } | bool isLegalAddImmediate(int64_t Imm) { return false; } | ||||
bool isLegalICmpImmediate(int64_t Imm) { return false; } | bool isLegalICmpImmediate(int64_t Imm) { return false; } | ||||
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, | bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, | ||||
bool HasBaseReg, int64_t Scale, | bool HasBaseReg, int64_t Scale, | ||||
unsigned AddrSpace) { | unsigned AddrSpace) { | ||||
// Guess that only reg and reg+reg addressing is allowed. This heuristic is | // Guess that only reg and reg+reg addressing is allowed. This heuristic is | ||||
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