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llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
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| 18 | #include "llvm/Analysis/TargetTransformInfo.h" | 18 | #include "llvm/Analysis/TargetTransformInfo.h" | ||
| 19 | #include "llvm/IR/CallSite.h" | 19 | #include "llvm/IR/CallSite.h" | ||
| 20 | #include "llvm/IR/DataLayout.h" | 20 | #include "llvm/IR/DataLayout.h" | ||
| 21 | #include "llvm/IR/Function.h" | 21 | #include "llvm/IR/Function.h" | ||
| 22 | #include "llvm/IR/GetElementPtrTypeIterator.h" | 22 | #include "llvm/IR/GetElementPtrTypeIterator.h" | ||
| 23 | #include "llvm/IR/Operator.h" | 23 | #include "llvm/IR/Operator.h" | ||
| 24 | #include "llvm/IR/Type.h" | 24 | #include "llvm/IR/Type.h" | ||
| 25 | #include "llvm/Analysis/VectorUtils.h" | 25 | #include "llvm/Analysis/VectorUtils.h" | ||
| 26 | #include "llvm/CodeGen/MachineBasicBlock.h" | ||||
| 27 | #include "llvm/CodeGen/MachineInstrBuilder.h" | ||||
| 28 | #include "llvm/Target/TargetInstrInfo.h" | ||||
| 29 | #include "llvm/Target/TargetSubtargetInfo.h" | ||||
| 26 | 30 | | |||
| 27 | namespace llvm { | 31 | namespace llvm { | ||
| 28 | 32 | | |||
| 29 | /// \brief Base class for use as a mix-in that aids implementing | 33 | /// \brief Base class for use as a mix-in that aids implementing | ||
| 30 | /// a TargetTransformInfo-compatible class. | 34 | /// a TargetTransformInfo-compatible class. | ||
| 31 | class TargetTransformInfoImplBase { | 35 | class TargetTransformInfoImplBase { | ||
| 32 | protected: | 36 | protected: | ||
| 33 | typedef TargetTransformInfo TTI; | 37 | typedef TargetTransformInfo TTI; | ||
| ▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Line(s) | 201 | if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" || | |||
| 201 | Name == "llabs") | 205 | Name == "llabs") | ||
| 202 | return false; | 206 | return false; | ||
| 203 | 207 | | |||
| 204 | return true; | 208 | return true; | ||
| 205 | } | 209 | } | ||
| 206 | 210 | | |||
| 207 | void getUnrollingPreferences(Loop *, TTI::UnrollingPreferences &) {} | 211 | void getUnrollingPreferences(Loop *, TTI::UnrollingPreferences &) {} | ||
| 208 | 212 | | |||
| 213 | void emitPatchableOp(StringRef, MachineBasicBlock &MBB, | ||||
| 214 | MachineBasicBlock::iterator &MBBI) const { | ||||
| 215 | auto *TII = MBB.getParent()->getSubtarget().getInstrInfo(); | ||||
| 216 | auto MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), | ||||
| 217 | TII->get(TargetOpcode::PATCHABLE_OP)) | ||||
| 218 | .addImm(2) | ||||
| 219 | .addImm(MBBI->getOpcode()); | ||||
| 220 | | ||||
| 221 | for (auto &MO : MBBI->operands()) | ||||
| 222 | MIB.addOperand(MO); | ||||
| 223 | | ||||
| 224 | MBBI->eraseFromParent(); | ||||
| 225 | } | ||||
| 226 | | ||||
| 209 | bool isLegalAddImmediate(int64_t Imm) { return false; } | 227 | bool isLegalAddImmediate(int64_t Imm) { return false; } | ||
| 210 | 228 | | |||
| 211 | bool isLegalICmpImmediate(int64_t Imm) { return false; } | 229 | bool isLegalICmpImmediate(int64_t Imm) { return false; } | ||
| 212 | 230 | | |||
| 213 | bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, | 231 | bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, | ||
| 214 | bool HasBaseReg, int64_t Scale, | 232 | bool HasBaseReg, int64_t Scale, | ||
| 215 | unsigned AddrSpace) { | 233 | unsigned AddrSpace) { | ||
| 216 | // Guess that only reg and reg+reg addressing is allowed. This heuristic is | 234 | // Guess that only reg and reg+reg addressing is allowed. This heuristic is | ||
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