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llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
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| Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines | AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, | ||||
| setOperationAction(ISD::ADDC, MVT::i64, Custom); | setOperationAction(ISD::ADDC, MVT::i64, Custom); | ||||
| setOperationAction(ISD::ADDE, MVT::i64, Custom); | setOperationAction(ISD::ADDE, MVT::i64, Custom); | ||||
| setOperationAction(ISD::SUBC, MVT::i64, Custom); | setOperationAction(ISD::SUBC, MVT::i64, Custom); | ||||
| setOperationAction(ISD::SUBE, MVT::i64, Custom); | setOperationAction(ISD::SUBE, MVT::i64, Custom); | ||||
| // AArch64 lacks both left-rotate and popcount instructions. | // AArch64 lacks both left-rotate and popcount instructions. | ||||
| setOperationAction(ISD::ROTL, MVT::i32, Expand); | setOperationAction(ISD::ROTL, MVT::i32, Expand); | ||||
| setOperationAction(ISD::ROTL, MVT::i64, Expand); | setOperationAction(ISD::ROTL, MVT::i64, Expand); | ||||
| for (MVT VT : MVT::vector_valuetypes()) { | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::ROTL, VT, Expand); | setOperationAction(ISD::ROTL, VT, Expand); | ||||
| setOperationAction(ISD::ROTR, VT, Expand); | setOperationAction(ISD::ROTR, VT, Expand); | ||||
| } | } | ||||
| // AArch64 doesn't have {U|S}MUL_LOHI. | // AArch64 doesn't have {U|S}MUL_LOHI. | ||||
| setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); | setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); | ||||
| setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); | setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); | ||||
| setOperationAction(ISD::CTPOP, MVT::i32, Custom); | setOperationAction(ISD::CTPOP, MVT::i32, Custom); | ||||
| setOperationAction(ISD::CTPOP, MVT::i64, Custom); | setOperationAction(ISD::CTPOP, MVT::i64, Custom); | ||||
| setOperationAction(ISD::SDIVREM, MVT::i32, Expand); | setOperationAction(ISD::SDIVREM, MVT::i32, Expand); | ||||
| setOperationAction(ISD::SDIVREM, MVT::i64, Expand); | setOperationAction(ISD::SDIVREM, MVT::i64, Expand); | ||||
| for (MVT VT : MVT::vector_valuetypes()) { | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::SDIVREM, VT, Expand); | setOperationAction(ISD::SDIVREM, VT, Expand); | ||||
| setOperationAction(ISD::UDIVREM, VT, Expand); | setOperationAction(ISD::UDIVREM, VT, Expand); | ||||
| } | } | ||||
| setOperationAction(ISD::SREM, MVT::i32, Expand); | setOperationAction(ISD::SREM, MVT::i32, Expand); | ||||
| setOperationAction(ISD::SREM, MVT::i64, Expand); | setOperationAction(ISD::SREM, MVT::i64, Expand); | ||||
| setOperationAction(ISD::UDIVREM, MVT::i32, Expand); | setOperationAction(ISD::UDIVREM, MVT::i32, Expand); | ||||
| setOperationAction(ISD::UDIVREM, MVT::i64, Expand); | setOperationAction(ISD::UDIVREM, MVT::i64, Expand); | ||||
| setOperationAction(ISD::UREM, MVT::i32, Expand); | setOperationAction(ISD::UREM, MVT::i32, Expand); | ||||
| ▲ Show 20 Lines • Show All 416 Lines • ▼ Show 20 Lines | for (MVT VT : { MVT::v4f16, MVT::v2f32, | ||||
| setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); | setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); | ||||
| setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); | setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); | ||||
| } | } | ||||
| setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); | setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); | ||||
| setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); | setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); | ||||
| // Likewise, narrowing and extending vector loads/stores aren't handled | // Likewise, narrowing and extending vector loads/stores aren't handled | ||||
| // directly. | // directly. | ||||
| for (MVT VT : MVT::vector_valuetypes()) { | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | ||||
| if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { | if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { | ||||
| setOperationAction(ISD::MULHS, VT, Legal); | setOperationAction(ISD::MULHS, VT, Legal); | ||||
| setOperationAction(ISD::MULHU, VT, Legal); | setOperationAction(ISD::MULHU, VT, Legal); | ||||
| } else { | } else { | ||||
| setOperationAction(ISD::MULHS, VT, Expand); | setOperationAction(ISD::MULHS, VT, Expand); | ||||
| setOperationAction(ISD::MULHU, VT, Expand); | setOperationAction(ISD::MULHU, VT, Expand); | ||||
| } | } | ||||
| setOperationAction(ISD::SMUL_LOHI, VT, Expand); | setOperationAction(ISD::SMUL_LOHI, VT, Expand); | ||||
| setOperationAction(ISD::UMUL_LOHI, VT, Expand); | setOperationAction(ISD::UMUL_LOHI, VT, Expand); | ||||
| setOperationAction(ISD::BSWAP, VT, Expand); | setOperationAction(ISD::BSWAP, VT, Expand); | ||||
| setOperationAction(ISD::CTTZ, VT, Expand); | setOperationAction(ISD::CTTZ, VT, Expand); | ||||
| for (MVT InnerVT : MVT::vector_valuetypes()) { | for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setTruncStoreAction(VT, InnerVT, Expand); | setTruncStoreAction(VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); | ||||
| } | } | ||||
| } | } | ||||
| // AArch64 has implementations of a lot of rounding-like FP operations. | // AArch64 has implementations of a lot of rounding-like FP operations. | ||||
| ▲ Show 20 Lines • Show All 11,578 Lines • Show Last 20 Lines | |||||