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llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
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| Show First 20 Lines • Show All 743 Lines • ▼ Show 20 Lines | for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, | ||||
| setOperationAction(ISD::FLOG10, VT, Expand); | setOperationAction(ISD::FLOG10, VT, Expand); | ||||
| setOperationAction(ISD::FEXP, VT, Expand); | setOperationAction(ISD::FEXP, VT, Expand); | ||||
| setOperationAction(ISD::FEXP2, VT, Expand); | setOperationAction(ISD::FEXP2, VT, Expand); | ||||
| } | } | ||||
| // First set operation action for all vector types to either promote | // First set operation action for all vector types to either promote | ||||
| // (for widening) or expand (for scalarization). Then we will selectively | // (for widening) or expand (for scalarization). Then we will selectively | ||||
| // turn on ones that can be effectively codegen'd. | // turn on ones that can be effectively codegen'd. | ||||
| for (MVT VT : MVT::vector_valuetypes()) { | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::SDIV, VT, Expand); | setOperationAction(ISD::SDIV, VT, Expand); | ||||
| setOperationAction(ISD::UDIV, VT, Expand); | setOperationAction(ISD::UDIV, VT, Expand); | ||||
| setOperationAction(ISD::SREM, VT, Expand); | setOperationAction(ISD::SREM, VT, Expand); | ||||
| setOperationAction(ISD::UREM, VT, Expand); | setOperationAction(ISD::UREM, VT, Expand); | ||||
| setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); | setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); | ||||
| setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); | setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); | ||||
| setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); | setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); | ||||
| setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); | setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); | ||||
| Show All 21 Lines | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::UINT_TO_FP, VT, Expand); | setOperationAction(ISD::UINT_TO_FP, VT, Expand); | ||||
| setOperationAction(ISD::SINT_TO_FP, VT, Expand); | setOperationAction(ISD::SINT_TO_FP, VT, Expand); | ||||
| setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand); | setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand); | ||||
| setOperationAction(ISD::TRUNCATE, VT, Expand); | setOperationAction(ISD::TRUNCATE, VT, Expand); | ||||
| setOperationAction(ISD::SIGN_EXTEND, VT, Expand); | setOperationAction(ISD::SIGN_EXTEND, VT, Expand); | ||||
| setOperationAction(ISD::ZERO_EXTEND, VT, Expand); | setOperationAction(ISD::ZERO_EXTEND, VT, Expand); | ||||
| setOperationAction(ISD::ANY_EXTEND, VT, Expand); | setOperationAction(ISD::ANY_EXTEND, VT, Expand); | ||||
| setOperationAction(ISD::SELECT_CC, VT, Expand); | setOperationAction(ISD::SELECT_CC, VT, Expand); | ||||
| for (MVT InnerVT : MVT::vector_valuetypes()) { | for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setTruncStoreAction(InnerVT, VT, Expand); | setTruncStoreAction(InnerVT, VT, Expand); | ||||
| setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand); | setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand); | ||||
| setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand); | setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand); | ||||
| // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like | // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like | ||||
| // types, we have to deal with them whether we ask for Expansion or not. | // types, we have to deal with them whether we ask for Expansion or not. | ||||
| // Setting Expand causes its own optimisation problems though, so leave | // Setting Expand causes its own optimisation problems though, so leave | ||||
| ▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines | for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { | ||||
| setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); | setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); | ||||
| } | } | ||||
| // We support custom legalizing of sext and anyext loads for specific | // We support custom legalizing of sext and anyext loads for specific | ||||
| // memory vector types which we can load as a scalar (or sequence of | // memory vector types which we can load as a scalar (or sequence of | ||||
| // scalars) and extend in-register to a legal 128-bit vector type. For sext | // scalars) and extend in-register to a legal 128-bit vector type. For sext | ||||
| // loads these must work with a single scalar load. | // loads these must work with a single scalar load. | ||||
| if (!ExperimentalVectorWideningLegalization) { | if (!ExperimentalVectorWideningLegalization) { | ||||
| for (MVT VT : MVT::integer_vector_valuetypes()) { | for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom); | ||||
| } | } | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines | if (!Subtarget.useSoftFloat() && Subtarget.hasSSE41()) { | ||||
| for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { | for (auto VT : { MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { | ||||
| setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); | setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); | ||||
| setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal); | setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal); | ||||
| } | } | ||||
| if (!ExperimentalVectorWideningLegalization) { | if (!ExperimentalVectorWideningLegalization) { | ||||
| // Avoid narrow result types when widening. The legal types are listed | // Avoid narrow result types when widening. The legal types are listed | ||||
| // in the next loop. | // in the next loop. | ||||
| for (MVT VT : MVT::integer_vector_valuetypes()) { | for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom); | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom); | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom); | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom); | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom); | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom); | ||||
| } | } | ||||
| } | } | ||||
| // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X | // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X | ||||
| for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) { | for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) { | ||||
| ▲ Show 20 Lines • Show All 45,348 Lines • Show Last 20 Lines | |||||