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llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
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| Show First 20 Lines • Show All 545 Lines • ▼ Show 20 Lines | if (Subtarget.use64BitRegs()) { | ||||
| setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); | setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); | ||||
| setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); | setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); | ||||
| setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); | setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); | ||||
| } | } | ||||
| if (Subtarget.hasAltivec()) { | if (Subtarget.hasAltivec()) { | ||||
| // First set operation action for all vector types to expand. Then we | // First set operation action for all vector types to expand. Then we | ||||
| // will selectively turn on ones that can be effectively codegen'd. | // will selectively turn on ones that can be effectively codegen'd. | ||||
| for (MVT VT : MVT::vector_valuetypes()) { | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| // add/sub are legal for all supported vector VT's. | // add/sub are legal for all supported vector VT's. | ||||
| setOperationAction(ISD::ADD, VT, Legal); | setOperationAction(ISD::ADD, VT, Legal); | ||||
| setOperationAction(ISD::SUB, VT, Legal); | setOperationAction(ISD::SUB, VT, Legal); | ||||
| // For v2i64, these are only valid with P8Vector. This is corrected after | // For v2i64, these are only valid with P8Vector. This is corrected after | ||||
| // the loop. | // the loop. | ||||
| if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) { | if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) { | ||||
| setOperationAction(ISD::SMAX, VT, Legal); | setOperationAction(ISD::SMAX, VT, Legal); | ||||
| ▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines | for (MVT VT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setOperationAction(ISD::SDIVREM, VT, Expand); | setOperationAction(ISD::SDIVREM, VT, Expand); | ||||
| setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); | setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); | ||||
| setOperationAction(ISD::FPOW, VT, Expand); | setOperationAction(ISD::FPOW, VT, Expand); | ||||
| setOperationAction(ISD::BSWAP, VT, Expand); | setOperationAction(ISD::BSWAP, VT, Expand); | ||||
| setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); | ||||
| setOperationAction(ISD::ROTL, VT, Expand); | setOperationAction(ISD::ROTL, VT, Expand); | ||||
| setOperationAction(ISD::ROTR, VT, Expand); | setOperationAction(ISD::ROTR, VT, Expand); | ||||
| for (MVT InnerVT : MVT::vector_valuetypes()) { | for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { | ||||
| setTruncStoreAction(VT, InnerVT, Expand); | setTruncStoreAction(VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); | setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); | ||||
| } | } | ||||
| } | } | ||||
| if (!Subtarget.hasP8Vector()) { | if (!Subtarget.hasP8Vector()) { | ||||
| setOperationAction(ISD::SMAX, MVT::v2i64, Expand); | setOperationAction(ISD::SMAX, MVT::v2i64, Expand); | ||||
| ▲ Show 20 Lines • Show All 14,778 Lines • Show Last 20 Lines | |||||