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llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines | MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM, | ||||
// Set up the register classes | // Set up the register classes | ||||
addRegisterClass(MVT::i32, &Mips::GPR32RegClass); | addRegisterClass(MVT::i32, &Mips::GPR32RegClass); | ||||
if (Subtarget.isGP64bit()) | if (Subtarget.isGP64bit()) | ||||
addRegisterClass(MVT::i64, &Mips::GPR64RegClass); | addRegisterClass(MVT::i64, &Mips::GPR64RegClass); | ||||
if (Subtarget.hasDSP() || Subtarget.hasMSA()) { | if (Subtarget.hasDSP() || Subtarget.hasMSA()) { | ||||
// Expand all truncating stores and extending loads. | // Expand all truncating stores and extending loads. | ||||
for (MVT VT0 : MVT::vector_valuetypes()) { | for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { | ||||
for (MVT VT1 : MVT::vector_valuetypes()) { | for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) { | ||||
setTruncStoreAction(VT0, VT1, Expand); | setTruncStoreAction(VT0, VT1, Expand); | ||||
setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); | setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); | ||||
setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); | setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); | ||||
setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); | setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); | ||||
} | } | ||||
} | } | ||||
} | } | ||||
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