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llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
| Show First 20 Lines • Show All 1,432 Lines • ▼ Show 20 Lines | if (Subtarget->is64Bit()) { | ||||
| addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); | addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); | ||||
| // ...but almost all operations must be expanded, so set that as | // ...but almost all operations must be expanded, so set that as | ||||
| // the default. | // the default. | ||||
| for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { | for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { | ||||
| setOperationAction(Op, MVT::v2i32, Expand); | setOperationAction(Op, MVT::v2i32, Expand); | ||||
| } | } | ||||
| // Truncating/extending stores/loads are also not supported. | // Truncating/extending stores/loads are also not supported. | ||||
| for (MVT VT : MVT::integer_vector_valuetypes()) { | for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { | ||||
| setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); | ||||
| setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); | setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); | ||||
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); | setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); | ||||
| setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); | setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); | ||||
| setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); | setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); | ||||
| setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); | setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); | ||||
| ▲ Show 20 Lines • Show All 1,970 Lines • Show Last 20 Lines | |||||