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llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
| Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines | public: | ||||
| /// \name Vector TTI Implementations | /// \name Vector TTI Implementations | ||||
| /// @{ | /// @{ | ||||
| bool useColdCCForColdCall(Function &F); | bool useColdCCForColdCall(Function &F); | ||||
| bool enableAggressiveInterleaving(bool LoopHasReductions); | bool enableAggressiveInterleaving(bool LoopHasReductions); | ||||
| TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, | TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, | ||||
| bool IsZeroCmp) const; | bool IsZeroCmp) const; | ||||
| bool enableInterleavedAccessVectorization(); | bool enableInterleavedAccessVectorization(); | ||||
| unsigned getNumberOfRegisters(bool Vector); | |||||
| enum PPCRegisterClass { | |||||
| GPRRC, FPRRC, VRRC, VSXRC | |||||
| }; | |||||
| unsigned getNumberOfRegisters(unsigned ClassID) const; | |||||
| unsigned getRegisterClassForType(Type *Ty, bool Vector) const; | |||||
| const char* getRegisterClassName(unsigned ClassID) const; | |||||
| unsigned getRegisterBitWidth(bool Vector) const; | unsigned getRegisterBitWidth(bool Vector) const; | ||||
| unsigned getCacheLineSize(); | unsigned getCacheLineSize(); | ||||
| unsigned getPrefetchDistance(); | unsigned getPrefetchDistance(); | ||||
| unsigned getMaxInterleaveFactor(unsigned VF); | unsigned getMaxInterleaveFactor(unsigned VF); | ||||
| int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2); | int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2); | ||||
| int getArithmeticInstrCost( | int getArithmeticInstrCost( | ||||
| unsigned Opcode, Type *Ty, | unsigned Opcode, Type *Ty, | ||||
| TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, | TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, | ||||
| Show All 26 Lines | |||||