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llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Lines | unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, | ||||
return TTI::TCC_Free; | return TTI::TCC_Free; | ||||
} | } | ||||
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, | unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, | ||||
Type *Ty) { | Type *Ty) { | ||||
return TTI::TCC_Free; | return TTI::TCC_Free; | ||||
} | } | ||||
unsigned getNumberOfRegisters(bool Vector) { return 8; } | unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; } | ||||
unsigned getRegisterClassForType(Type *Ty, bool Vector) const { | |||||
return Vector ? 1 : 0; | |||||
}; | |||||
const char* getRegisterClassName(unsigned ClassID) const { | |||||
switch (ClassID) { | |||||
default: | |||||
return "Generic::Unknown Register Class"; | |||||
case 0: return "Generic::ScalarRC"; | |||||
case 1: return "Generic::VectorRC"; | |||||
} | |||||
} | |||||
unsigned getRegisterBitWidth(bool Vector) const { return 32; } | unsigned getRegisterBitWidth(bool Vector) const { return 32; } | ||||
unsigned getMinVectorRegisterBitWidth() { return 128; } | unsigned getMinVectorRegisterBitWidth() { return 128; } | ||||
bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; } | bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; } | ||||
unsigned getMinimumVF(unsigned ElemWidth) const { return 0; } | unsigned getMinimumVF(unsigned ElemWidth) const { return 0; } | ||||
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