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llvm/include/llvm/CodeGen/TargetRegisterInfo.h
| Show First 20 Lines • Show All 371 Lines • ▼ Show 20 Line(s) | 258 | public: | |||
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| 372 | /// MaskB = getSubRegIndexLaneMask(SubB); | 372 | /// MaskB = getSubRegIndexLaneMask(SubB); | ||
| 373 | /// | 373 | /// | ||
| 374 | /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by | 374 | /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by | ||
| 375 | /// SubB. | 375 | /// SubB. | ||
| 376 | LaneBitmask getCoveringLanes() const { return CoveringLanes; } | 376 | LaneBitmask getCoveringLanes() const { return CoveringLanes; } | ||
| 377 | 377 | | |||
| 378 | /// Returns true if the two registers are equal or alias each other. | 378 | /// Returns true if the two registers are equal or alias each other. | ||
| 379 | /// The registers may be virtual registers. | 379 | /// The registers may be virtual registers. | ||
| 380 | bool regsOverlap(unsigned regA, unsigned regB) const { | 380 | bool regsOverlap(Register regA, Register regB) const { | ||
| 381 | if (regA == regB) return true; | 381 | if (regA == regB) return true; | ||
| 382 | if (Register::isVirtualRegister(regA) || Register::isVirtualRegister(regB)) | 382 | if (regA.isVirtual() || regB.isVirtual()) | ||
| 383 | return false; | 383 | return false; | ||
| 384 | 384 | | |||
| 385 | // Regunits are numerically ordered. Find a common unit. | 385 | // Regunits are numerically ordered. Find a common unit. | ||
| 386 | MCRegUnitIterator RUA(regA, this); | 386 | MCRegUnitIterator RUA(regA, this); | ||
| 387 | MCRegUnitIterator RUB(regB, this); | 387 | MCRegUnitIterator RUB(regB, this); | ||
| 388 | do { | 388 | do { | ||
| 389 | if (*RUA == *RUB) return true; | 389 | if (*RUA == *RUB) return true; | ||
| 390 | if (*RUA < *RUB) ++RUA; | 390 | if (*RUA < *RUB) ++RUA; | ||
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| 1143 | /// The format is: | 1143 | /// The format is: | ||
| 1144 | /// %noreg - NoRegister | 1144 | /// %noreg - NoRegister | ||
| 1145 | /// %5 - a virtual register. | 1145 | /// %5 - a virtual register. | ||
| 1146 | /// %5:sub_8bit - a virtual register with sub-register index (with TRI). | 1146 | /// %5:sub_8bit - a virtual register with sub-register index (with TRI). | ||
| 1147 | /// %eax - a physical register | 1147 | /// %eax - a physical register | ||
| 1148 | /// %physreg17 - a physical register when no TRI instance given. | 1148 | /// %physreg17 - a physical register when no TRI instance given. | ||
| 1149 | /// | 1149 | /// | ||
| 1150 | /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; | 1150 | /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; | ||
| 1151 | Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, | 1151 | Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr, | ||
| 1152 | unsigned SubIdx = 0, | 1152 | unsigned SubIdx = 0, | ||
| 1153 | const MachineRegisterInfo *MRI = nullptr); | 1153 | const MachineRegisterInfo *MRI = nullptr); | ||
| 1154 | 1154 | | |||
| 1155 | /// Create Printable object to print register units on a \ref raw_ostream. | 1155 | /// Create Printable object to print register units on a \ref raw_ostream. | ||
| 1156 | /// | 1156 | /// | ||
| 1157 | /// Register units are named after their root registers: | 1157 | /// Register units are named after their root registers: | ||
| 1158 | /// | 1158 | /// | ||
| 1159 | /// al - Single root. | 1159 | /// al - Single root. | ||
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