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llvm/include/llvm/CodeGen/LiveIntervals.h
| Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Line(s) | 105 | static float getSpillWeight(bool isDef, bool isUse, | |||
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| 106 | const MachineBlockFrequencyInfo *MBFI, | 106 | const MachineBlockFrequencyInfo *MBFI, | ||
| 107 | const MachineInstr &MI); | 107 | const MachineInstr &MI); | ||
| 108 | 108 | | |||
| 109 | /// Calculate the spill weight to assign to a single instruction. | 109 | /// Calculate the spill weight to assign to a single instruction. | ||
| 110 | static float getSpillWeight(bool isDef, bool isUse, | 110 | static float getSpillWeight(bool isDef, bool isUse, | ||
| 111 | const MachineBlockFrequencyInfo *MBFI, | 111 | const MachineBlockFrequencyInfo *MBFI, | ||
| 112 | const MachineBasicBlock *MBB); | 112 | const MachineBasicBlock *MBB); | ||
| 113 | 113 | | |||
| 114 | LiveInterval &getInterval(unsigned Reg) { | 114 | LiveInterval &getInterval(Register Reg) { | ||
| 115 | if (hasInterval(Reg)) | 115 | if (hasInterval(Reg)) | ||
| 116 | return *VirtRegIntervals[Reg]; | 116 | return *VirtRegIntervals[Reg.id()]; | ||
| 117 | else | 117 | else | ||
| 118 | return createAndComputeVirtRegInterval(Reg); | 118 | return createAndComputeVirtRegInterval(Reg); | ||
| 119 | } | 119 | } | ||
| 120 | 120 | | |||
| 121 | const LiveInterval &getInterval(unsigned Reg) const { | 121 | const LiveInterval &getInterval(Register Reg) const { | ||
| 122 | return const_cast<LiveIntervals*>(this)->getInterval(Reg); | 122 | return const_cast<LiveIntervals*>(this)->getInterval(Reg); | ||
| 123 | } | 123 | } | ||
| 124 | 124 | | |||
| 125 | bool hasInterval(unsigned Reg) const { | 125 | bool hasInterval(Register Reg) const { | ||
| 126 | return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; | 126 | return VirtRegIntervals.inBounds(Reg.id()) && | ||
| 127 | VirtRegIntervals[Reg.id()]; | ||||
| 127 | } | 128 | } | ||
| 128 | 129 | | |||
| 129 | /// Interval creation. | 130 | /// Interval creation. | ||
| 130 | LiveInterval &createEmptyInterval(unsigned Reg) { | 131 | LiveInterval &createEmptyInterval(Register Reg) { | ||
| 131 | assert(!hasInterval(Reg) && "Interval already exists!"); | 132 | assert(!hasInterval(Reg) && "Interval already exists!"); | ||
| 132 | VirtRegIntervals.grow(Reg); | 133 | VirtRegIntervals.grow(Reg.id()); | ||
| 133 | VirtRegIntervals[Reg] = createInterval(Reg); | 134 | VirtRegIntervals[Reg.id()] = createInterval(Reg); | ||
| 134 | return *VirtRegIntervals[Reg]; | 135 | return *VirtRegIntervals[Reg.id()]; | ||
| 135 | } | 136 | } | ||
| 136 | 137 | | |||
| 137 | LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) { | 138 | LiveInterval &createAndComputeVirtRegInterval(Register Reg) { | ||
| 138 | LiveInterval &LI = createEmptyInterval(Reg); | 139 | LiveInterval &LI = createEmptyInterval(Reg); | ||
| 139 | computeVirtRegInterval(LI); | 140 | computeVirtRegInterval(LI); | ||
| 140 | return LI; | 141 | return LI; | ||
| 141 | } | 142 | } | ||
| 142 | 143 | | |||
| 143 | /// Interval removal. | 144 | /// Interval removal. | ||
| 144 | void removeInterval(unsigned Reg) { | 145 | void removeInterval(unsigned Reg) { | ||
| 145 | delete VirtRegIntervals[Reg]; | 146 | delete VirtRegIntervals[Reg]; | ||
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