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llvm/include/llvm/CodeGen/LiveIntervals.h
Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | static float getSpillWeight(bool isDef, bool isUse, | ||||
const MachineBlockFrequencyInfo *MBFI, | const MachineBlockFrequencyInfo *MBFI, | ||||
const MachineInstr &MI); | const MachineInstr &MI); | ||||
/// Calculate the spill weight to assign to a single instruction. | /// Calculate the spill weight to assign to a single instruction. | ||||
static float getSpillWeight(bool isDef, bool isUse, | static float getSpillWeight(bool isDef, bool isUse, | ||||
const MachineBlockFrequencyInfo *MBFI, | const MachineBlockFrequencyInfo *MBFI, | ||||
const MachineBasicBlock *MBB); | const MachineBasicBlock *MBB); | ||||
LiveInterval &getInterval(unsigned Reg) { | LiveInterval &getInterval(Register Reg) { | ||||
if (hasInterval(Reg)) | if (hasInterval(Reg)) | ||||
return *VirtRegIntervals[Reg]; | return *VirtRegIntervals[Reg.id()]; | ||||
else | else | ||||
return createAndComputeVirtRegInterval(Reg); | return createAndComputeVirtRegInterval(Reg); | ||||
} | } | ||||
const LiveInterval &getInterval(unsigned Reg) const { | const LiveInterval &getInterval(Register Reg) const { | ||||
return const_cast<LiveIntervals*>(this)->getInterval(Reg); | return const_cast<LiveIntervals*>(this)->getInterval(Reg); | ||||
} | } | ||||
bool hasInterval(unsigned Reg) const { | bool hasInterval(Register Reg) const { | ||||
return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; | return VirtRegIntervals.inBounds(Reg.id()) && | ||||
VirtRegIntervals[Reg.id()]; | |||||
} | } | ||||
/// Interval creation. | /// Interval creation. | ||||
LiveInterval &createEmptyInterval(unsigned Reg) { | LiveInterval &createEmptyInterval(Register Reg) { | ||||
assert(!hasInterval(Reg) && "Interval already exists!"); | assert(!hasInterval(Reg) && "Interval already exists!"); | ||||
VirtRegIntervals.grow(Reg); | VirtRegIntervals.grow(Reg.id()); | ||||
VirtRegIntervals[Reg] = createInterval(Reg); | VirtRegIntervals[Reg.id()] = createInterval(Reg); | ||||
return *VirtRegIntervals[Reg]; | return *VirtRegIntervals[Reg.id()]; | ||||
} | } | ||||
LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) { | LiveInterval &createAndComputeVirtRegInterval(Register Reg) { | ||||
LiveInterval &LI = createEmptyInterval(Reg); | LiveInterval &LI = createEmptyInterval(Reg); | ||||
computeVirtRegInterval(LI); | computeVirtRegInterval(LI); | ||||
return LI; | return LI; | ||||
} | } | ||||
/// Interval removal. | /// Interval removal. | ||||
void removeInterval(unsigned Reg) { | void removeInterval(unsigned Reg) { | ||||
delete VirtRegIntervals[Reg]; | delete VirtRegIntervals[Reg]; | ||||
▲ Show 20 Lines • Show All 348 Lines • Show Last 20 Lines |