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llvm/lib/Target/ARM/ARMISelLowering.cpp
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| Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Line(s) | 214 | void ARMTargetLowering::addDRTypeForNEON(MVT VT) { | |||
|---|---|---|---|---|---|
| 216 | addTypeForNEON(VT, MVT::f64, MVT::v2i32); | 216 | addTypeForNEON(VT, MVT::f64, MVT::v2i32); | ||
| 217 | } | 217 | } | ||
| 218 | 218 | | |||
| 219 | void ARMTargetLowering::addQRTypeForNEON(MVT VT) { | 219 | void ARMTargetLowering::addQRTypeForNEON(MVT VT) { | ||
| 220 | addRegisterClass(VT, &ARM::DPairRegClass); | 220 | addRegisterClass(VT, &ARM::DPairRegClass); | ||
| 221 | addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); | 221 | addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); | ||
| 222 | } | 222 | } | ||
| 223 | 223 | | |||
| 224 | void ARMTargetLowering::addMVEVectorTypes() { | ||||
| 225 | // We 'support' these types up to bitcast/load/store level, regardless of | ||||
| 226 | // MVE integer-only / float support. Only doing FP data processing on the FP | ||||
| 227 | // vector types is inhibited at integer-only level. | ||||
| 228 | | ||||
| 229 | const MVT VecTypes[] = { | ||||
| 230 | MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8, | ||||
| 231 | MVT::v2f64, MVT::v4f32, MVT::v8f16, | ||||
| 232 | }; | ||||
| 233 | | ||||
| 234 | for (auto VT : VecTypes) { | ||||
| 235 | addRegisterClass(VT, &ARM::QPRRegClass); | ||||
| 236 | for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) | ||||
| 237 | setOperationAction(Opc, VT, Expand); | ||||
| 238 | setOperationAction(ISD::BITCAST, VT, Legal); | ||||
| 239 | setOperationAction(ISD::LOAD, VT, Legal); | ||||
| 240 | setOperationAction(ISD::STORE, VT, Legal); | ||||
| 241 | } | ||||
| 242 | } | ||||
| 243 | | ||||
| 224 | ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, | 244 | ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, | ||
| 225 | const ARMSubtarget &STI) | 245 | const ARMSubtarget &STI) | ||
| 226 | : TargetLowering(TM), Subtarget(&STI) { | 246 | : TargetLowering(TM), Subtarget(&STI) { | ||
| 227 | RegInfo = Subtarget->getRegisterInfo(); | 247 | RegInfo = Subtarget->getRegisterInfo(); | ||
| 228 | Itins = Subtarget->getInstrItineraryData(); | 248 | Itins = Subtarget->getInstrItineraryData(); | ||
| 229 | 249 | | |||
| 230 | setBooleanContents(ZeroOrOneBooleanContent); | 250 | setBooleanContents(ZeroOrOneBooleanContent); | ||
| 231 | setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); | 251 | setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); | ||
| ▲ Show 20 Lines • Show All 273 Lines • ▼ Show 20 Line(s) | 511 | if (Subtarget->isTargetAEABI()) { | |||
| 505 | } | 525 | } | ||
| 506 | } | 526 | } | ||
| 507 | 527 | | |||
| 508 | if (Subtarget->isThumb1Only()) | 528 | if (Subtarget->isThumb1Only()) | ||
| 509 | addRegisterClass(MVT::i32, &ARM::tGPRRegClass); | 529 | addRegisterClass(MVT::i32, &ARM::tGPRRegClass); | ||
| 510 | else | 530 | else | ||
| 511 | addRegisterClass(MVT::i32, &ARM::GPRRegClass); | 531 | addRegisterClass(MVT::i32, &ARM::GPRRegClass); | ||
| 512 | 532 | | |||
| 513 | if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() && | 533 | if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() && | ||
| 514 | !Subtarget->isThumb1Only()) { | 534 | !Subtarget->isThumb1Only()) { | ||
| 515 | addRegisterClass(MVT::f32, &ARM::SPRRegClass); | 535 | addRegisterClass(MVT::f32, &ARM::SPRRegClass); | ||
| 516 | addRegisterClass(MVT::f64, &ARM::DPRRegClass); | 536 | addRegisterClass(MVT::f64, &ARM::DPRRegClass); | ||
| 517 | } | 537 | } | ||
| 518 | 538 | | |||
| 519 | if (Subtarget->hasFullFP16()) { | 539 | if (Subtarget->hasFullFP16()) { | ||
| 520 | addRegisterClass(MVT::f16, &ARM::HPRRegClass); | 540 | addRegisterClass(MVT::f16, &ARM::HPRRegClass); | ||
| 521 | setOperationAction(ISD::BITCAST, MVT::i16, Custom); | 541 | setOperationAction(ISD::BITCAST, MVT::i16, Custom); | ||
| Show All 21 Lines | |||||
| 543 | } | 563 | } | ||
| 544 | 564 | | |||
| 545 | setOperationAction(ISD::ConstantFP, MVT::f32, Custom); | 565 | setOperationAction(ISD::ConstantFP, MVT::f32, Custom); | ||
| 546 | setOperationAction(ISD::ConstantFP, MVT::f64, Custom); | 566 | setOperationAction(ISD::ConstantFP, MVT::f64, Custom); | ||
| 547 | 567 | | |||
| 548 | setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); | 568 | setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); | ||
| 549 | setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); | 569 | setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); | ||
| 550 | 570 | | |||
| 571 | if (Subtarget->hasMVEIntegerOps()) | ||||
| 572 | addMVEVectorTypes(); | ||||
| 573 | | ||||
| 551 | if (Subtarget->hasNEON()) { | 574 | if (Subtarget->hasNEON()) { | ||
| 552 | addDRTypeForNEON(MVT::v2f32); | 575 | addDRTypeForNEON(MVT::v2f32); | ||
| 553 | addDRTypeForNEON(MVT::v8i8); | 576 | addDRTypeForNEON(MVT::v8i8); | ||
| 554 | addDRTypeForNEON(MVT::v4i16); | 577 | addDRTypeForNEON(MVT::v4i16); | ||
| 555 | addDRTypeForNEON(MVT::v2i32); | 578 | addDRTypeForNEON(MVT::v2i32); | ||
| 556 | addDRTypeForNEON(MVT::v1i64); | 579 | addDRTypeForNEON(MVT::v1i64); | ||
| 557 | 580 | | |||
| 558 | addQRTypeForNEON(MVT::v4f32); | 581 | addQRTypeForNEON(MVT::v4f32); | ||
| 559 | addQRTypeForNEON(MVT::v2f64); | 582 | addQRTypeForNEON(MVT::v2f64); | ||
| 560 | addQRTypeForNEON(MVT::v16i8); | 583 | addQRTypeForNEON(MVT::v16i8); | ||
| 561 | addQRTypeForNEON(MVT::v8i16); | 584 | addQRTypeForNEON(MVT::v8i16); | ||
| 562 | addQRTypeForNEON(MVT::v4i32); | 585 | addQRTypeForNEON(MVT::v4i32); | ||
| 563 | addQRTypeForNEON(MVT::v2i64); | 586 | addQRTypeForNEON(MVT::v2i64); | ||
| 564 | 587 | | |||
| 565 | if (Subtarget->hasFullFP16()) { | 588 | if (Subtarget->hasFullFP16()) { | ||
| 566 | addQRTypeForNEON(MVT::v8f16); | 589 | addQRTypeForNEON(MVT::v8f16); | ||
| 567 | addDRTypeForNEON(MVT::v4f16); | 590 | addDRTypeForNEON(MVT::v4f16); | ||
| 568 | } | 591 | } | ||
| 592 | } | ||||
| 569 | 593 | | |||
| 594 | if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) { | ||||
| 570 | // v2f64 is legal so that QR subregs can be extracted as f64 elements, but | 595 | // v2f64 is legal so that QR subregs can be extracted as f64 elements, but | ||
| 571 | // neither Neon nor VFP support any arithmetic operations on it. | 596 | // none of Neon, MVE or VFP supports any arithmetic operations on it. | ||
| 572 | // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively | | |||
| 573 | // supported for v4f32. | | |||
| 574 | setOperationAction(ISD::FADD, MVT::v2f64, Expand); | 597 | setOperationAction(ISD::FADD, MVT::v2f64, Expand); | ||
| 575 | setOperationAction(ISD::FSUB, MVT::v2f64, Expand); | 598 | setOperationAction(ISD::FSUB, MVT::v2f64, Expand); | ||
| 576 | setOperationAction(ISD::FMUL, MVT::v2f64, Expand); | 599 | setOperationAction(ISD::FMUL, MVT::v2f64, Expand); | ||
| 577 | // FIXME: Code duplication: FDIV and FREM are expanded always, see | 600 | // FIXME: Code duplication: FDIV and FREM are expanded always, see | ||
| 578 | // ARMTargetLowering::addTypeForNEON method for details. | 601 | // ARMTargetLowering::addTypeForNEON method for details. | ||
| 579 | setOperationAction(ISD::FDIV, MVT::v2f64, Expand); | 602 | setOperationAction(ISD::FDIV, MVT::v2f64, Expand); | ||
| 580 | setOperationAction(ISD::FREM, MVT::v2f64, Expand); | 603 | setOperationAction(ISD::FREM, MVT::v2f64, Expand); | ||
| 581 | // FIXME: Create unittest. | 604 | // FIXME: Create unittest. | ||
| Show All 17 Lines | |||||
| 599 | setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); | 622 | setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); | ||
| 600 | // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR. | 623 | // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR. | ||
| 601 | setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); | 624 | setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); | ||
| 602 | setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); | 625 | setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); | ||
| 603 | setOperationAction(ISD::FRINT, MVT::v2f64, Expand); | 626 | setOperationAction(ISD::FRINT, MVT::v2f64, Expand); | ||
| 604 | setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); | 627 | setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); | ||
| 605 | setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); | 628 | setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); | ||
| 606 | setOperationAction(ISD::FMA, MVT::v2f64, Expand); | 629 | setOperationAction(ISD::FMA, MVT::v2f64, Expand); | ||
| 630 | } | ||||
| 607 | 631 | | |||
| 632 | if (Subtarget->hasNEON()) { | ||||
| 633 | // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively | ||||
| 634 | // supported for v4f32. | ||||
| 608 | setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); | 635 | setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); | ||
| 609 | setOperationAction(ISD::FSIN, MVT::v4f32, Expand); | 636 | setOperationAction(ISD::FSIN, MVT::v4f32, Expand); | ||
| 610 | setOperationAction(ISD::FCOS, MVT::v4f32, Expand); | 637 | setOperationAction(ISD::FCOS, MVT::v4f32, Expand); | ||
| 611 | setOperationAction(ISD::FPOW, MVT::v4f32, Expand); | 638 | setOperationAction(ISD::FPOW, MVT::v4f32, Expand); | ||
| 612 | setOperationAction(ISD::FLOG, MVT::v4f32, Expand); | 639 | setOperationAction(ISD::FLOG, MVT::v4f32, Expand); | ||
| 613 | setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); | 640 | setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); | ||
| 614 | setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); | 641 | setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); | ||
| 615 | setOperationAction(ISD::FEXP, MVT::v4f32, Expand); | 642 | setOperationAction(ISD::FEXP, MVT::v4f32, Expand); | ||
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| 1035 | 1062 | | |||
| 1036 | // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. | 1063 | // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. | ||
| 1037 | if (!Subtarget->hasV6Ops()) { | 1064 | if (!Subtarget->hasV6Ops()) { | ||
| 1038 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); | 1065 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); | ||
| 1039 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); | 1066 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); | ||
| 1040 | } | 1067 | } | ||
| 1041 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); | 1068 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); | ||
| 1042 | 1069 | | |||
| 1043 | if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() && | 1070 | if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() && | ||
| 1044 | !Subtarget->isThumb1Only()) { | 1071 | !Subtarget->isThumb1Only()) { | ||
| 1045 | // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR | 1072 | // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR | ||
| 1046 | // iff target supports vfp2. | 1073 | // iff target supports vfp2. | ||
| 1047 | setOperationAction(ISD::BITCAST, MVT::i64, Custom); | 1074 | setOperationAction(ISD::BITCAST, MVT::i64, Custom); | ||
| 1048 | setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); | 1075 | setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); | ||
| 1049 | } | 1076 | } | ||
| 1050 | 1077 | | |||
| 1051 | // We want to custom lower some of our intrinsics. | 1078 | // We want to custom lower some of our intrinsics. | ||
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